The newest cell phones rely on processors with maximum operating speeds of 500 MHz. Compare this with earlier versions of GSM-only phones that operated at less than 50 MHz, and it's easy to see how far the industry has come. Earlier mobile phones were heavily modem oriented, i.e. making and receiving a call was the only major processor load.
With the constant introduction of different frequency bands, new standards, and converging applications — camera, WLAN, multimedia messaging, video — comes the need for faster and, in most cases, multiple processors. Typically, one processor dedicates itself to the modem (which is increasingly more complex with multi-standard), while the other processors handle the various other features and applications, which are often designed specifically around their unique system requirements. If you extrapolate the curve and requirements further out, it makes a lot of sense to assume that before long, cell phones will be using 1-GHz processors. Fig. 1 shows the typical functions available in today's cell phones.
High-speed processors are required to run the large amount of software within a defined time. It is a simple mathematical formula: as you double the processor power the amount of code carried out is doubled. The amount of code is proportional to the amount of functions being carried out by the processor.
As mentioned earlier the cell phone is increasing in functionality and the expectation of the user is higher speed, or — more importantly from a perceptional point of view — the instant operation of the function. The cell phone could, in some cases, be expected to take a picture and relay the information back to the display while scanning the network for GSM, EDGE, and CDMA base stations.
Higher speed does solve the problem. However, as speed increases so does the power associated with the processor. Transistor speed is linked to power. This model is already seen in the laptop market, with most PCs having additional fans and heat sinks to enable the multiple gigahertz performance.
Unfortunately, this is not the solution for the cell-phone manufacturer, as the cell phone is still tied electrically to a battery in a way that laptops are not. Laptops are still managed by plugging into an ac-dc converter power block: though they are designed for portability, it is still for only periods of two to three hours. Cell phones are expected to last in standby mode for several days, and in talk and operational modes for lengths of time that are at least comparable with a laptop (i.e., two-to-three hours).
Simply said, the processor or processors in cell phones are going to be a limiting factor in the future, and though the software partitioning and the investments made by major cell-phone providers will increase to overcome this problem there is no simple and clean answer.
Today's 90-nm IC processes are now becoming dated technology, although it was the mainstream several years ago. With the introduction of smaller geometries, the power-budget constraints have moved from the device delay to the interconnect delays. With 65-nm technology starting to ramp, no longer is dynamic power the dominant factor, but rather leakage current. This power is likely lost without any benefit to the system.
Typically, a cell-phone manufacturer will want no more than 5% of the full operational power lost. But with deep micron technologies, more than 50% of the power is lost to interconnect leakage.
There is a growing emphasis now for multi-core architectures and it is an important trend to participate in and follow. Power leakage is actually reduced with multi-core technology because of the breaking apart of significant and very power-hungry functions. You have a fixed area of die, and you could either make a single core, with fast memory and caches, or use the real estate for two or more cores.
At lower operating frequencies and with the same aggregate throughput, multi-cores are also useful for separating the functions of the mobile phone. One core could be used for modem functions, another for multimedia functions. Partitioning in this way is a more efficient technique for saving power, optimizing software usage, reducing required space, and minimizing complexity.
However, the ways in which manufacturers are designing dual cores are different. Some are designing for two completely separate voltage rails; others are designing for single voltage rails. This leaves a somewhat complex situation for designing the power-management chip, as the sum of the cores is either shared across two devices or consumed in one device.
Many cell-phone designs have sent out mixed messages about what is needed. However, it is clear that they all need fast, dynamic voltage control. Due to the latency of the I2C interface, in some cases other approaches are preferred due to the faster attributed speed of changes in the output voltage. Still, a more traditional approach using I2C could also be used in cases where the outputs are needed to change slower, closer microprocessors.
The amount of current needed in these dual cores is associated to the maximum peak currents of each of the other cores separately. So even though partitioning of the functions saves power, the maximum peak current could, in theory, be the sum of the peaks. For the power-management designer, this means high currents are possible. It should not be seen in the same way, though, as the pulses of current from the power amplifier in the GSM chain. This can occur where 2 A are needed for transmitting to the base station and long distances from the receiver. This condition can exist, but needs to be planned and designed for by the system engineer.
Application processors should be considered differently from the core processors discussed above. This has a lot to do with the fact that they are designed for a specific function, and though they can be expected to work fast and efficiently, they have lower current needs. Also, voltages on these cores need to be scaled, as they are typically “ON” when they are needed to be “OFF” after a particular function has been completed, such as in the case of a GPS processor or a Bluetooth processor. What becomes important for an application processor's dc-dc converters is the absolute space available for integration. Though larger-geometry technologies are used for application processors, they tend to lag behind the core processors due to factors like operating frequency or sometimes even the component supplier.
The holy grail of questions for the dc-dc design engineer is where to optimize the efficiency to obtain the best performance. The reality is that even with the constraints of leakage current, thermal concerns, battery capacity, and integration of additional features, there is a desire for the device to offer the best performance across the whole band. While being realistic about the many requirements, it still remains possible to estimate where efficiency would be most critical.
Leakage currents of most modern high-performance processors are typically in the region of 5 mA, and the operational standby currents of most applications are less than 10 mA. The processor will spend more time in this mode of operation than anywhere else. It is very difficult to estimate exact numbers as it is highly dependent on the design, functionality, and software used in the cell phone. For example, two suppliers could be using exactly the same processors, but how they partition their software could affect the current draw and the timing.
The pie chart in Fig. 2 is a representation of what a typical power supply could be expected to deliver with respect to time. As shown, the power supply spends the majority of its time in the minimum leakage-current regions of 500 µA to 10 mA and between 50 and 300 mA. The lower region is the highest because the majority of the time the cell phone is in standby mode; that is, sitting on the desk with the display turned off, occasionally signaling the base station for location and strength indications.
Because of the need for efficiency in this region, techniques like PWM have not been used within dc-dc converters due to the efficiencies associated with the scheme. PFM has been used at lower currents because its efficiency is higher. Also, due to the need for currents as low as 500 µA, quiescent current is important because it also impacts efficiency. Customer use also affects quiescent current because the dc-dc converter could be on constantly, with the device drawing current for sustained periods of time.
However, efficiencies are typically above 70 % during operational modes within the lower current regions (including quiescent current). This occurs because the time spent in the lower regions of the operating system takes its toll on the total system budget. This is important for our customers and likely a target area for performance enhancement. When the dc-dc converter is in this lower current range, the dynamic performance requirements are lowest. In sleep mode, effectively, the currents cycle slowly based on factors other than the demands of operation.
When the cell phone starts to operate, it typically requires a significant percentage of its components to work. To operate a call the power amplifier, microphone, speaker driver, mixed-signal, RF, processor, and auxiliary functions are needed. These functions typically draw in excess of 50 mA, and the higher currents are for the pulses of the power amplifier.
In this area of operation, dynamic performance increases and is often the most demanding. Full operation of PWM would be preferred, which can provide excellent transient performance.
For higher currents in the above-500-mA range this is normally caused by spikes from heavy loading of software and hardware. This is more typical of functions such as video, gaming, and, in the future, for camera flash and audio — although these will likely be handled by 5-V rails and supercapacitors.
Though it is highly likely that the system will need to budget for these currents, the actual time a user will spend downloading and playing multimedia functions is much smaller than the operation of the modem and standby modes of the phone. Also these peaks in themselves are somewhat rare.
Efficiencies during these peaks are as much a factor of thermal constraints as they are an absolute efficiency for battery life unless, in the future, the very nature of cell-phone usage changes and it becomes more of a multimedia hub first and a modem second. It is likely that some models will be this way.
Current profiles of future dc-dc converters will include the ability to consume the minimum area associated with the function possible without impacting thermal constraints; having high efficiency in the lower and mid-current ranges; and the ability to adapt its dynamic performance based on the current profile, likely exhibiting sleep modes, normal operational, and high-speed modes.
As discussed earlier, processors used in future will be faster, and though techniques like dual processors, co-processors, applications processors, and software partitioning will be used to save power and manage the applications, the fact remains that the amount of processing expected in the future will increase. This is the same with dc-dc converters: higher operating frequency reduces the external component size; frequency will be used in processors to handle the larger quantities of software.
Processor speed will have a great impact in the future on critical system factors other than efficiency, current profiling, and size. To recap, efficiency is needed because of the constraints of battery technology, high levels of integration, and the subsequent demands on power. Current profiling is needed because of the time the device will remain in specific areas of output current. Again, size is another factor, as cell-phone manufacturers must keep the phone small and attractive to the consumer while increasing the phone's level of integration and features.
If we consider some very specific situations that relate to customer requirements today regarding processor speed, many of the future processors will have sleep modes to conserve power. This translates into the ability to dynamically select output voltages to the requirements of the processor. Simply in high-speed mode the voltage will be higher, and in slow-speed mode the voltage will be lower.
Our customers are discussing the use of either Vselects or I2C for this. It is becoming clear that in some cases the I2C is not fast enough to change the voltage due to the latency of the control. To have the system acknowledge the need for the change, a microprocessor can be used to send a software command to the required address.
Customers will use Vselects in some cases where they need the voltage to change faster. This in itself puts pressure on the Vselects. As processor speeds increase, the dc-dc converter of the future will likely need to change even faster between voltages. Industry numbers are now less than 100 µs. Expect this to be less than 10 µs in three to four years. All this will be needed within the tighter constraints of VOUT and transient overshoots and undershoots.
The very nature of transients will change in the future. As the processor speeds increase, the effect will be the device beginning to manipulate the software at a higher speed, meaning steeper slew rates. What tends to happen in a processor is when it starts to work there are many blocks that wake up. This is not always in parallel; in some cases they need to be done in serial. So, the positive and negative slew rates will likely be different.
When the device is switched “OFF” and the blocks all switch “OFF”, they do so instantaneously to save as much power as possible, so the negative slew rates are likely to be faster. Due to system requirements, though, in cases where sleep mode is entered and all the constraints of VOUT are maintained, undershoots and overshoots need to be within the specifications. Industry numbers for slew rates are approximately 100 µs for typically large positive and negative steps.
Customer operations are making decisions for their power supplies with a positive step of 100 µs and a negative step of 25 µs. We should expect the steps to migrate faster in the future, but exact numbers are difficult to speculate. Because slew rates have increased 10x over the last four years, we should expect at least a 5x increase over the next four years. There will certainly be some give, and maybe faster negative than positive slew rates, but surely both will be faster.
Start-up time is somewhat different, as this is heavily dependent on the application that the dc-dc converter is working with. As most processors will be either asleep or active all the time, the need for faster active or asleep dc-dc converters will be matched to the system needs of the processor and the time it takes for the software to be loaded, etc. However, if the converter takes more time, this must be translated into the number of clock cycles the processor has lost to begin its operation.