One of the key challenges when designing a constant-on-time (COT) buck converter is to make it stable with low-ESR output capacitors. Although the basic theory of voltage-mode hysteric converters expects the output voltage will be greater after turning on the high-side switch, it shows a limited cycle oscillation on the output if the ESR of the output capacitor (ESRo) is not enough to meet this expectation (Fig. 1). Such a limited cycle oscillation should be prohibited, even if it is not catastrophic, to maintain output quality.
EMULATED RIPPLE INJECTION CIRCUIT
Although there are devices manufactured by some semiconductor manufacturers that generate emulated ripple within the IC, most COT converters, on behalf of ESRo, require external emulated ripple injection (ERI) to be compatible with low ESR output capacitors. This article aims to help designers select components not only for preventing limited cycle oscillation but for optimizing ERI circuitry performance.
In the frequency domain, ERI makes a similar response in the high-frequency range around the switching frequency, similar to how the ESRo makes a zero in that range. It also shows different responses with ESRo in the low-frequency range. Consequently, its total frequency response differs somewhat compared to just the ESR zero (Fig. 2).
In the time domain, a fast response when the load changes from light to heavy can be achieved when the COT converter exhibits its maximum bandwidth, defined by fixed on-time and minimum off-time during TR (Fig. 3). So, it is required to analyze the sensed voltage on feedback (V FB) during load transient in the time domain.
Fig. 4 shows the output-stage circuit — including ERI — assuming a low-ESR capacitor and a low-DCR inductor. For the worst-case analysis, no-load and zero-ESR is considered. Therefore, the phase-shift at the corner frequency of the output filter is 180 °. To find the V SW to VO transfer function, VSW can be divided into a voltage-controlled current-source IL and a voltage-controlled voltage-source VO (Fig. 5),
Based on superposition theory, the IL to VFB transfer function can be calculated after shorting voltage source VO, and the VO to VFB transfer function can be calculated after opening the current source IL.
Consequently, the sum of the outputs is:
and its double-pole frequency is:
The definitions of GHF(s), GLF(s), RF, and AF are:
AMOUNT OF EMULATED RIPPLE
Where, GHF(s) has two poles. Its higher-frequency pole is:
and the lower-frequency pole is:
In the high-frequency range, GHF(s) is dominant because its order of numerator is larger than the order of denominator. The eESR, the amount of emulated ripple on VFB in the scale of ESR, can be represented as:
MAKE NO PHASE-LEAD OF eESR(s) AT FSW
GHF(s) has a phase shift which starts from -90° to -270°, whereas GLF(s) has one zero and one pole. Unless placing FP1 below or:
PREVENT LIMITED CYCLE OSCILLATION
GHF(s) creates additional phase shift which results in surplus oscillation on the output because the phase is dominated by the bigger gain transfer function between GHF(s) and GLF(s). Approximately, the criterion for dominating GLF(s) at FDP is:
eESR(s) has one double zero at its origin and two separated poles. eESR(s) can act as a pure resistive impedance if it has no phase-lead at FSW. It is possible to place FP1 below FSW/10. Such a phase-lead at FSW makes the small falling slope of emulated ripple, which results in larger jitter. Assuming FP1 is below FSW/10, eESR(s) at FSW can be simplified as:
Based on COT theory, to prevent limited cycle oscillation:
DISPLAY MAXIMUM BANDWIDTH WHEN LOAD CHANGES
Considering the feedback-resistor-divider's attenuation, the criteria to prevent limited cycle oscillation becomes:
From Eq. 15, we may select an excessively small RRCR, as it does not have a negative effect on output ripple, but such a large emulated ripple results in poor line regulation and load transient. Some devices normally require 15 to 30 mV of minimum ripple (VminRIPPLE) on the feedback node to minimize jitter on the switch node and ensure noise immunity. The criterion to minimize jitter and ensure noise immunity is:
In the time domain, our focus will be to minimize the overshoot/undershoot when there are sudden changes in load current. Assuming the load changes from light to heavy, such a fast transient response can be achieved as VERI — consequently VFB — dominantly follows VO rather than VCR, so the sum of VO and VCR (VERI = VCR + VO) is less than the reference voltage during TR (Fig. 3). To ensure V ERI dominantly follows VO during TR:
The criteria to ensure VERI dominantly follows VO when the load changes from heavy to light is:
is the averaged slope of IL during TR during light to heavy load changes.
is the slope of IL during heavy to light load changes.
is the minimum off-time of the IC.
IminSTEP, the load step during load transient, should be selected as a minimum load step in a considerable load-step range because after optimizing, the converter will show its max bandwidth if the load step is bigger than IminSTEP, but cannot show its max bandwidth if the load step is smaller than IminSTEP. Setting IminSTEP as half the max load current is a good starting point.
Figs. 6a to 6c show output voltage with a load transient. While enough ripple to prevent limited cycle oscillation is injected in all cases, Fig. 6c limits oscillation, undershoot/overshoot due to limited bandwidth, and unwanted oscillation due to phase shift that can be cleared by optimizing external components.
LM3100/LM3150 datasheet, National Semiconductor, http://www.national.com
LM5008/LM34919 datasheet, same as above
“Fundamentals of Power Electronics”, Robert W. Erickson