One of the key challenges when designing a constantontime (COT) buck converter is to make it stable with lowESR output capacitors. Although the basic theory of voltagemode hysteric converters expects the output voltage will be greater after turning on the highside switch, it shows a limited cycle oscillation on the output if the ESR of the output capacitor (ESRo) is not enough to meet this expectation (Fig. 1). Such a limited cycle oscillation should be prohibited, even if it is not catastrophic, to maintain output quality.
EMULATED RIPPLE INJECTION CIRCUIT
Although there are devices manufactured by some semiconductor manufacturers that generate emulated ripple within the IC^{[1]}, most COT converters, on behalf of ESRo, require external emulated ripple injection (ERI) to be compatible with low ESR output capacitors^{[2]}. This article aims to help designers select components not only for preventing limited cycle oscillation but for optimizing ERI circuitry performance.
In the frequency domain, ERI makes a similar response in the highfrequency range around the switching frequency, similar to how the ESRo makes a zero in that range. It also shows different responses with ESRo in the lowfrequency range. Consequently, its total frequency response differs somewhat compared to just the ESR zero (Fig. 2).
In the time domain, a fast response when the load changes from light to heavy can be achieved when the COT converter exhibits its maximum bandwidth, defined by fixed ontime and minimum offtime during T_{R} (Fig. 3). So, it is required to analyze the sensed voltage on feedback (V _{FB}) during load transient in the time domain.
Fig. 4 shows the outputstage circuit — including ERI — assuming a lowESR capacitor and a lowDCR inductor. For the worstcase analysis, noload and zeroESR is considered. Therefore, the phaseshift at the corner frequency of the output filter is 180 °. To find the V _{SW} to V_{O} transfer function, V_{SW} can be divided into a voltagecontrolled currentsource I_{L} and a voltagecontrolled voltagesource V_{O} (Fig. 5),
where:
and
Based on superposition theory, the I_{L} to V_{FB} transfer function can be calculated after shorting voltage source V_{O}, and the V_{O} to V_{FB} transfer function can be calculated after opening the current source I_{L}.
Consequently, the sum of the outputs is:
and its doublepole frequency is:
The definitions of G_{HF}(s), G_{LF}(s), R_{F}, and A_{F} are:
AMOUNT OF EMULATED RIPPLE
Where, G_{HF}(s) has two poles. Its higherfrequency pole is:
and the lowerfrequency pole is:
In the highfrequency range, G_{HF}(s) is dominant because its order of numerator is larger than the order of denominator. The eESR, the amount of emulated ripple on V_{FB} in the scale of ESR, can be represented as:
MAKE NO PHASELEAD OF eESR(s) AT F_{SW}
G_{HF}(s) has a phase shift which starts from 90° to 270°, whereas G_{LF}(s) has one zero and one pole. Unless placing F_{P1} below or:
PREVENT LIMITED CYCLE OSCILLATION
G_{HF}(s) creates additional phase shift which results in surplus oscillation on the output because the phase is dominated by the bigger gain transfer function between G_{HF}(s) and G_{LF}(s). Approximately, the criterion for dominating G_{LF}(s) at F_{DP} is:
eESR(s) has one double zero at its origin and two separated poles. eESR(s) can act as a pure resistive impedance if it has no phaselead at F_{SW}. It is possible to place F_{P1} below F_{SW}/10. Such a phaselead at F_{SW} makes the small falling slope of emulated ripple, which results in larger jitter. Assuming F_{P1} is below F_{SW}/10, eESR(s) at F_{SW} can be simplified as:
Based on COT theory, to prevent limited cycle oscillation:
DISPLAY MAXIMUM BANDWIDTH WHEN LOAD CHANGES
Considering the feedbackresistordivider's attenuation, the criteria to prevent limited cycle oscillation becomes:
From Eq. 15, we may select an excessively small R_{R}C_{R}, as it does not have a negative effect on output ripple, but such a large emulated ripple results in poor line regulation and load transient. Some devices normally require 15 to 30 mV of minimum ripple (V_{minRIPPLE}) on the feedback node to minimize jitter on the switch node and ensure noise immunity. The criterion to minimize jitter and ensure noise immunity is:
In the time domain, our focus will be to minimize the overshoot/undershoot when there are sudden changes in load current. Assuming the load changes from light to heavy, such a fast transient response can be achieved as V_{ERI} — consequently V_{FB} — dominantly follows V_{O} rather than V_{CR}, so the sum of V_{O} and V_{CR} (V_{ERI} = V_{CR} + V_{O}) is less than the reference voltage during T_{R} (Fig. 3). To ensure V _{ERI} dominantly follows V_{O} during T_{R}:
Alternatively,
The criteria to ensure V_{ERI} dominantly follows V_{O} when the load changes from heavy to light is:
Alternatively,
Where
is the averaged slope of I_{L} during T_{R} during light to heavy load changes.
is the slope of I_{L} during heavy to light load changes.
EXPERIMENTAL RESULTS
is the minimum offtime of the IC.
REFERENCES
I_{minSTEP}, the load step during load transient, should be selected as a minimum load step in a considerable loadstep range because after optimizing, the converter will show its max bandwidth if the load step is bigger than I_{minSTEP}, but cannot show its max bandwidth if the load step is smaller than I_{minSTEP}. Setting I_{minSTEP} as half the max load current is a good starting point.
Figs. 6a to 6c show output voltage with a load transient. While enough ripple to prevent limited cycle oscillation is injected in all cases, Fig. 6c limits oscillation, undershoot/overshoot due to limited bandwidth, and unwanted oscillation due to phase shift that can be cleared by optimizing external components.
Summary of Design Criteria for External Ripple Injection

LM3100/LM3150 datasheet, National Semiconductor, http://www.national.com

LM5008/LM34919 datasheet, same as above

“Fundamentals of Power Electronics”, Robert W. Erickson