AC-rectified power sources with capacitive filtering draw high-amplitude discontinuous currents, resulting in poor power factor and a power line rich in harmonics and high circulating currents. Poor power factor and high line-current harmonics can cause overheating of transformers and inductive equipment, degradation of system voltages, and increased stress on components due to higher peak currents. In addition, stringent limits imposed on harmonic currents by international standards and regulatory bodies make the need to improve power quality even more important. Power-factor correction (PFC) is the solution to this problem.
Traditionally, PFC has been implemented with a standard analog controller that worked on average current-mode control. A better approach is to use two or more multiphased or interleaved boost converters to achieve PFC. This approach offers the advantages of a reduction in conduction losses for each converter, allowing for smaller inductors that are capable of carrying higher ripple current, better transient response, and reduced current harmonics.
The challenges involved when interleaving two converters include the requirement of complex circuits for load balancing or current sharing, and generating a phase shift between the two converters. In addition, the offset and gain errors that occur in analog circuits also lead to difficulties in PFC implementation. On the other hand, a digital implementation eliminates the above challenges and offers advantages such as ease of development and the possibility of integrating multiple features on a single chip. We will describe the digital implementation of a two-phase interleaved PFC converter using a digital signal controller (DSC).
To describe this implementation of interleaved PFC, we have to define some related terminology. Active power is the power that is actually consumed and registered on an electric meter at the consumer's location, and is expressed in kW.
Total power is the apparent power, expressed in kVA, which includes the reactive power that does no useful work, but is required to sustain the magnetic field associated with the inductive equipment. Implementing PFC reshapes the input current from the source to be similar to its input voltage; that is, in addition to regulating the output voltage.
Among the commonly encountered problems for a single-stage PFC are:
TWO-PHASE INTERLEAVED PFC
- Ripple cancellation is not possible.
- Difficulty in balancing the currents when two converters are paralleled.
- Large inductor volume
The interleaved PFC requires five input signals to implement the control algorithm, as indicated in Fig. 1. The DSC generates pulses PWM1 and PWM2 to control the two PFC converters after acquiring the three feedback signals: the rectified input voltage (V AC), the rectified input current (IAC) and the dc bus voltage (VDC). Implementing the PFC requires these three feedback signals, even for a single-stage converter.
In the case of a two-phase interleaved PFC converter where two such stages are involved, the two switch currents, IM1 and IM2, also need to be monitored for load sharing. The boost converter is the best-suited topology when using PFC converters because of the absence of crossover distortions, as well as the viability of operating the converter in continuous conduction mode.
Fig. 2 shows the interface of a two-phase interleaved PFC converter with a DSC. When two boost converters operate 180° out of phase, the sum of the two inductor currents, I L1 and IL2, on the input side is the total input current, IAC, drawn from the source.
Ripple currents in the two inductors will also be out of phase so they cancel each other out and reduce the total ripple current on the input. A duty cycle of 50% provides the best possible cancellation of ripple currents.
DIGITAL COMPENSATOR DESIGN OF INTERLEAVED PFC
On the output side, the sum of the two diode currents, ID1 and ID2, minus the output current, ILOAD, is the current through the output capacitor, CO. At duty cycles of 0%, 50%, and 100%, the output capacitor only has to filter out the inductor ripple current. Hence, the output capacitor ripple is also significantly reduced, but as a function of the duty cycle. This reduction of ripple current on the inductors and capacitors tends to improve the overall efficiency of the system.
In a DSC-based application, the relevant analog parameters and the control loops have to be redefined and made discrete. This enables an easier and more logical changeover from existing hardware to the digital counterpart.
Referring to Fig. 3, the compensators used in this application are based on proportional-integral (PI) controllers that are implemented digitally. Several control loops are involved in the digital interleaved PFC design.
The outer loop in the control system is the voltage control loop, which regulates the output voltage with any changes in the input voltage and the load. The inputs to the voltage loop are the reference dc voltage, VDCREF, and the sensed dc voltage, VDC. The voltage error compensator produces a control output so that the dc bus voltage remains constant at the reference value VDCREF.
The voltage control-loop output is a control signal determining the reference current, IACREF, for the current control loop. The voltage control loop executes at a rate of 2 kHz, and its bandwidth is selected to be 10 Hz.
By selecting a 10-Hz bandwidth, the voltage loop will not react much to the 100- or 120-Hz waveshape. This ensures that the output of the voltage compensator is a dc-like signal, and helps in retaining the shape of the current wave when multiplied by a sine reference. The zero bandwidth is chosen to be 1/5 to 1/4 of the voltage-loop bandwidth. This is to ensure that the roots of the characteristic equation governing the voltage compensator are well separated.
The current control loop is the inner loop of the control system that is required to make the inductor current, IAC, track the rectified input voltage, VAC. The inputs to the current loop are the reference current signal, IACREF, and the input current, IAC. The current error compensator corrects the error between these two currents and produces an output so that the input current, IAC, follows the reference current, IACREF.
The current control loop executes at a rate of 50 kHz and its bandwidth is selected to be between 4 kHz to 6 kHz, for a switching frequency of 100 kHz. This will aid the current, IAC, in faithfully tracking the rectified input voltage, VAC.
The current control loop bandwidth and the execution rate should be much faster than that of the voltage control loop because it has to correctly track the semi-sinusoidal waveform, which is at twice the input frequency. The zero bandwidth is chosen to be 1/5 to 1/4 of the current-loop bandwidth, so that the roots of the characteristics equation governing the current compensator are well separated.
There are two boost converters interleaved together, so there will be small differences and drifts in the individual output voltages resulting from the internal characteristics of the MOSFETs, and the internal resistances of the inductors, capacitors, and diodes. This scenario calls for a load-balance control loop, the main purpose of which is to balance the currents in the two boost-converter switches, which in turn results in the load being shared by the two converters equally.
The output of the current control loop decides the inductor voltage and, hence, duty cycle ‘D’ is needed as an input to the load-balance control loop. The load-balance control loop mainly corrects the difference between the MOSFET currents (IM1 - IM2) and brings it close to the reference input, which is zero.
INPUT AND OUTPUT VOLTAGE DECOUPLING LOOP
The output of the load-balance control loop will be a duty-correction term, ΔD, which is either added or subtracted to/from the main duty cycle, D, to get the individual boost duty cycles, D1 and D2. The rate of execution of the load-balance control loop is chosen to be 2 kHz, and its bandwidth is chosen to be about 200 Hz, since it has to balance only the average currents flowing through the two boost converters.
One of the requirements of interleaved PFC is to regulate the output dc voltage, even with variations in the input voltage. In order to take care of any sudden variations in the input voltage, the decoupling of the system from the input voltage is required.
By applying Kirchhoff's laws in the boost converter circuit, we arrive at Eq. 1:
VL = Inductor voltage obtained from the current error compensator
D = Duty cycle of the MOSFET
INTERLEAVING TWO OR MORE STAGES
The individual duty cycles for the boost converters are derived from the load correction term of the load-balance compensator.
The value of the inductor is chosen based on the amount of ripple current that must be tolerated. In a single-stage PFC converter, for a given power level and switching frequency, the energy stored in the inductor is given by:
where L is the inductance, based on the amount of ripple current, ΔI.
In a two-stage interleaved PFC converter, for the same power level and switching frequency, the energy stored in the inductors is given by:
(See equation 5)
The inductance for each stage is 2L, because the ripple current in each stage is taken to be half that of the single-stage PFC converter. Because of interleaving, the ripple currents tend to cancel out and, hence, we get better performance for the same component size.
Therefore, we can relax on the ripple-current requirement of the individual stages by tolerating more ripple. This reduces the inductance required for each of the stages. If we elect for the ripple current to be twice that of previous case, then the energy stored in the inductors becomes:
(See equation 6)
For a given ripple content on the ac-line current, the inductor size can be significantly reduced by interleaving two boost converters. Conversely, for a given inductor size, the ripple currents can be significantly reduced by interleaving converters. This helps in reducing the cost and also in improving the efficiency of the system.
Microchip Technology App. Note #AN1106, “Power Factor Correction in Power Conversion Applications Using the dsPIC® DSC,” by Vinaya Skanda Nagaraj.
Microchip Technology App. Note #AN1208, “Integrated Power Factor Correction (PFC) and Sensorless Field Oriented Control (FOC) System,” by Vinaya Skanda Nagaraj. Note: dsPIC is a registered trademark of Microchip Technology Inc.