The IES5501 from Integrated Electronic Solutions extends and expands 2-wire bus systems, such as PMBus and SMBus, using analog IC design principles. The IC extends the bus load limit by buffering the clock (SCL) and data (SDA) lines.
Low input-to-output offset voltages allow the ICs to be daisy chained or star-configured. The design of the part enables level shifting of bus voltages between 1.8 V and 15 V. Rise time accelerators are not used. The devices also feature low standby current, low noise susceptibility, and the ability to plug into live backplanes.
Samples of the IES5501 are offered in 8-pin SO and 8-pin DIP packages. Production devices will be released in 8-pin SO and 8-pin MSOP packages.