Frequently, the lowest possible cost is the fundamental challenge that engineers encounter when designing power converters. When multiple output voltages are required, it is often tempting to provide one switching regulator for each output voltage. While this approach provides excellent output-voltage regulation, it certainly does nothing to help achieve the top design priority — lowest possible cost.
Fortunately, circuits such as coupled inductors and charge pumps can be easily implemented in traditional switching converters to provide additional output-voltage rails at minimal cost. Using the proper circuit configuration, it is often possible to achieve good voltage regulation along with high efficiency.
Fig. 1 shows three different ways to generate an auxiliary output from a coupled inductor. In all three configurations, current flows in the auxiliary winding only during the on time of the synchronous FET. During this period of the switching cycle, the VOUT1 output voltage plus the drain-to-source voltage (VGS) drop of the synchronous FET are impressed across the inductor's primary winding. The FET's voltage drop generally is quite small, usually less than 0.1 V, compared to around 0.5 V if a diode rectifier is used.
The auxiliary output voltage for an inductor with a 1:1 winding ratio is equal to the primary-winding voltage, less the forward-voltage drop of the secondary-side diode, or VOUT2 = VOUT1 + VFET - VD. The actual VOUT2 output voltage obtained is dependent on the load currents in both outputs since the voltage drops of VFET and VD are current dependent. Additionally, good coupling between the windings is necessary to reduce leakage-inductance effects at higher operating frequencies. Lower switching frequencies and light loading provide the best voltage regulation for VOUT2.
As shown in Fig. 1, the ground reference of the auxiliary winding can be connected to any point. In circuit A, the VOUT2 ground can be connected to a separate, isolated ground (as shown) or to the VOUT1 ground if isolation is not required. In circuit B, the VOUT2 ground floats on top of VOUT1, making the output of VOUT2 approximately twice that of VOUT1. In circuit C, the diode's cathode is grounded, making VOUT2 a negative output voltage.
Fig. 2 shows an example of an isolated coupled inductor design that uses a linear regulator (U2) to provide a low-current, low-noise, well-regulated output voltage. Standard off-the-shelf coupled inductors are typically bifilar wound and have 1:1 turn ratios. Low-cost custom magnetics also can be easily designed and quickly obtained, providing an avenue for generating unusual turn ratios or multiple output voltages.
Fig. 3 shows an example of a multiple-winding coupled inductor that provides matching positive and negative auxiliary output voltages (VOUT2 and VOUT3). Various voltage configurations can be implemented by using the circuit grounding arrangements shown in Fig. 1.
While diode rectification on the secondary side of the coupled inductor is easy to implement, the forward-voltage drop of the diode can introduce a large output-voltage variation over load current and temperature. Fig. 4 shows a circuit that uses secondary-side synchronous rectification to reduce the voltage variation and FET losses.
When low-resistance FETs are used, FET voltage drops are minimal and the output-voltage regulation for VOUT2 improves. Under certain loading conditions, the voltage drops of FETs Q1 and Q2 will perfectly cancel each other, resulting in an output voltage for VOUT2 that is equal to VOUT1 times the turns ratio of the coupled inductor.
Excellent cross regulation and high efficiency can be achieved with this technique. The drawback is that access to the low-side FET gate-drive signal is required to drive the synchronous coupled-inductor FET. This eliminates the use of synchronous buck controllers that have integrated top and bottom FETs. The circuit in Fig. 5 bypasses this limitation by using a p-channel FET.
The Fig. 5 circuit operates identically to that of Fig. 4, except the gate drive to the p-channel FET is driven out-of-phase by the switch node, rather than the bottom FET gate drive. Care must be taken when a p-channel FET is used in this configuration that the gate-source voltage available is adequate to ensure full enhancement in steady-state operation.
The maximum turn-on VGS in Fig. 5 is equal to VOUT2, since the FET switches on when the switch node pulls to ground. This places a limit on the maximum output voltage that VOUT2 can be, as many p-channel FETs have maximum VGS ratings of only 8 V or 12 V. A maximum reverse VGS equal to the input voltage (VIN) is applied when the switch node pulls to the input voltage and the output voltage is zero, which occurs at startup.
Fig. 6 shows a synchronous version of the circuit shown in Fig. 1c, using an n-channel FET for the auxiliary output. The gate-drive voltage for Q3 is derived from the gate-drive voltage of bottom FET Q2, allowing both FETs to switch in phase with each other. Capacitor C1 ac-couples this switching signal, but blocks its dc average level. Diode D1 conducts only during the negative swing of the Q2 drive voltage, clamping Q3's gate voltage to 0.7 V below the source and turning it off.
During the positive swing of the Q2 drive voltage, VGS for Q3 is equal to the Q2 gate-drive voltage, less a diode drop, turning it on. The use of 2.5-VGS threshold parts may be necessary if the gate-drive voltage is 4.5 V to 5 V. Without D1, the positive VGS would vary with duty cycle, creating a situation where FET Q3 may not have enough drive voltage to turn on properly.
The circuit in Fig. 7 is a boost converter with a charge pump that generates a negative auxiliary output voltage. The charge-pump circuit is composed of C2, C4, D3 and D4. When the FET turns off in a boost converter, the stored energy in the inductor is transferred to the output capacitor and load through diodes D1 and D2. At the same time, D4 conducts and C2 is charged to the output voltage plus a diode drop.
When the FET turns on again, the voltage on C2 pulls the charge-pump output negative through D3. The two diodes in the boost converter (D1 and D2) are necessary to cancel the forward-voltage drops of the two diodes in the charge pump (D3 and D4). Excellent voltage regulation is achieved for light loads on the (negative) charge-pump output.
The circuit in Fig. 8 is a charge pump that boosts the VOUT2 output voltage to the input voltage plus the VOUT1 output voltage. When the internal synchronous FET of the TPS62007 controller switches to ground, it charges C3 to the VOUT1 output voltage, less one diode drop. Then the internal control FET turns on, pulling U1 pin 9 to VIN. This action forces the charge stored in C3 into output-capacitor C5.
As with most charge pumps, there are two diode drop reductions in the output voltage in Fig . 8. This circuit is useful in applications where the input voltage is well regulated or where the auxiliary output can feed the input to a linear regulator for a lower output voltage.
Fig. 9 is a variation of Fig. 8, but provides a negative output voltage at VOUT2. The output voltage of the charge pump is equal to the inverted input voltage, less two diode drops.
The circuit in Fig. 10 is a multiple-output flyback using a stacked-winding transformer. Regulation is achieved by feedback from output VOUT2. The addition of diode D1 and C9 creates a negative-output VOUT4 that is equal in magnitude to VOUT2.
Energy is transferred to all outputs only during the off time of FET Q1. During this interval, a negative voltage equal to VOUT2 is imposed across the primary winding, due to a 1:1 turns ratio between the primary winding and the VOUT2 stacked winding. With a negative VOUT2 clamped across the primary winding, diode D1 charges capacitor C9, resulting in a voltage on output VOUT4 that is closely matched to VOUT2.