When system design engineers are in search of power for mixed-signal electronics, they must satisfy performance, cost, efficiency and space requirements. Electronic equipment such as rack-mount servers, communication equipment, laptops and many consumer electronic goods must conserve space to maintain the form factor of the product. Certain features and specifications of power controller ICs can help satisfy system specifications and enhance the performance of the power supply and the load.
Key controller features and specs include adjustable switching frequency, feedback voltage accuracy, startup tracking, power sequencing, prebiased startup, the ability to work with an external reference and the ability to synchronize to an external clock. When optimized, these features can reduce electromagnetic interference (EMI), transient response times, transient voltage amplitudes, solution size, output capacitance requirements and overall bill-of-materials costs.
A user-adjustable switching frequency allows power designer to set the oscillator switching frequency to achieve the desired filter component size and, consequently, the solution size. A high switching frequency reduces the power-solution footprint by decreasing the size of the charge storage components. This includes input/output capacitors, inductors and other filtering components.
By moving from a 100-kHz to a 1-MHz switching frequency, the typical inductance required decreases tenfold while the volume of the inductor decreases fivefold. (The comparison was done with two shielded drum-core inductors of the same series, with saturation levels 15% apart from each other, with the inductor current ripple set to 30% of the maximum load current and with the following application power parameters: VIN = 12 V, VOUT = 3.3 V, ILOAD = 5 A, as shown in Fig. 1.)
Shielded drum-core inductors are a good choice for switch-mode power supplies (SMPS) that require an inductance value between 0.33 μH and 1 mH. These inductors are appropriate for high-frequency, low-EMI and low-cost applications.
The output capacitor also decreases in size as the switching frequency increases. Assume that we have selected multilayer ceramic capacitors (MLCCs) for the output filter and that the equivalent series resistance (ESR) is low enough that the output-voltage ripple is capacitive. A SMPS design with a 100-kHz switching frequency, a 1.5-A peak-to-peak ac current and a 50-mV output-voltage ripple requires 37.5-μF capacitance. The typical capacitance requirement decreases tenfold when operating at a 1-MHz switching frequency, and the case-size transitions from a 1210 MLCC to a 0603 case representing almost a 20-times reduction in volume.
In this example, the design for the output filter components only considered voltage and current ripple without examination of load and line transients. The availability of external compensation gives the power-supply designer the flexibility to optimize the feedback loop without oversizing the output capacitance.
For example, to decrease the output-voltage transient, designers can take advantage of the wide gain-bandwidth product of the error amplifier. A high closed-loop-bandwidth frequency decreases the time needed for the error amplifier to react to load and line transients. As a typical rule of thumb, a bandwidth designed at one-tenth to one-fifth of the switching frequency results in a high performance loop response.
Fig. 2 and Fig. 3 show the result of increasing the bandwidth. The SMPSs underwent the same test conditions: equal slew rates, 350-mA to 8-A load transient step, 440-μF output capacitance and equal feedback-loop-gain phase margin (48 degrees).
In the example, the output-voltage transient decreased by approximately ±80 mV. The external compensation provides the flexibility to fine-tune the speed of the loop response while maintaining the same output capacitance.
Feedback Voltage Accuracy
The demand for faster processing speeds, conservation of battery life and thermal considerations have driven digital processors to decrease their operating voltage. To maintain predictable logic-level states, it is particularly significant for the SMPS to have tight feedback-voltage accuracy across an extended die temperature range of -40°C to 125 °C. Capacitance reduction is also feasible when using a ±1% feedback accuracy device over ±2% devices.
According to field-programmable gate-array power requirements, an output-voltage response to a line or load transient must not exceed ±5% of the nominal 1.2-V supply voltage. With a ± 2% dc accuracy device, this leaves the output-voltage supply with only ±36 mV of allowable voltage swing. With a device with a dc accuracy of ±1%, the allowable output-voltage budget is now wider at ±48 mV.
In a typical example as shown in Fig. 4 and Fig. 5, based on a 350-mA to 6-A load transient response, equal loop-gain bandwidth and phase margin, a 1% device accuracy over a 2% device realizes a 50% reduction in output capacitance. A tighter feedback-voltage accuracy specification can translate to lower-value capacitors, saving cost and total solution size.
Tracking and Precision-Enable Features
Modern mixed-signal systems require multiple voltage-supply rails, which power the processor core, I/O, and other analog and digital circuits. Each voltage rail calls for a different voltage and load rating. The startup timing of each voltage rail, in reference to each other, is a critical requirement. Keeping the voltage differential minimized during powerup and/or keeping them sequenced will prevent latchup, bus contention and undesirable transistor logic states.
The precision-enable feature provides sequential timing necessary for proper startup. A second method of sequencing is the tracking feature. Tracking gives control to the master power supply over the slave’s startup rise time.
Two common tracking methods are: ratio metric, where the supply voltages reach their regulation point at the same time, and simultaneous startup, where the supply voltages increase with equal slew rates, as shown in Fig. 6 and Fig. 7, respectively. Tracking and precision-enable allows several voltage rails to reach their nominal voltages within a specified target time.
Prebiased Startup Feature
In reference to the SMPS, prebiased startup is defined as starting up into a biased output rail. Common output-voltage prebiased situations include redundant power supplies, multiphase voltage-regulators modules, or cycling of the SMPS under no-load or light-load conditions.
Discharging the output capacitor may lead to conditions such as the voltage and current of one rail sneaking into the output of another rail through a parasitic p-n junction, which potentially may cause the leakage component to fail. Other loads may trigger the output power-good flag, output undervoltage protection and/or the output current protection of the voltage regulator IC.
In many situations, accidentally discharging a prebiased load on the output rail of a SMPS is not acceptable. Only regulators with synchronous rectification have the ability to discharge the output capacitor in a prebiased condition through the low-side MOSFET. Synchronous SMPS equipped with soft-start prebiased circuitry are able to sustain a charged output capacitor during the power-up period. This feature prevents the inadvertent discharge of the output rail during a prebias startup.
External Reference Feature
Regulators with an external reference feature can be advantageous in specific applications. One example is in meeting DDR and DDR2 SDRAM termination specifications. DDR and DDR2 memory require a single power source for primary supply voltages (VDD) to ensure that all voltage levels track each other, which is especially critical during powerup.
At initial powerup, all supply power should be stable and meet specification timing. The external reference voltage is expected to equal one-half VDD and must track variations in the dc voltage level. Fig. 8 shows a typical application circuit for a DDR2 solution.
Data communication and high-quality audio and video electronics require low noise to maintain uncompromised signal integrity. Typically, a single-rail bus supplies power to multiple SMPS, which subsequently provide voltage rails to a number of electronic components in a system.
Beat noise occurs when two or more SMPS are connected to the same input supply or when the input of one SMPS connects to the output of another SMPS. The sum and difference between switching frequencies of nonsynchronized SMPS will develop beat frequencies. The power supplies will reflect beat noise to the input bus and conduct into any electrical circuit connected to it, such as other SMPS.
Techniques used to attenuate the beat noise include:
- Additional filtering at the front end of each switching regulator
- Increasing the loop gain sufficiently at the beat frequency in order to reject the input to output-noise transfer
- Setting the switching frequency of one of the SMPS to switch at two times greater than the second SMPS.
These techniques increase the solution size and/or increase design time. A better alternative involves synchronizing the SMPS oscillators. Synchronizing two or more internal oscillators will theoretically eliminate beat noise and relieve conducted noise interaction with other loads. Synchronizing also keeps the generated EMI to a predictable set of frequencies, as illustrated in Fig. 9 and Fig. 10.