Designers of today's networking equipment are being pushed to increase the data throughput and performance of their systems, as well as add functionality and features that differentiate them from competitors. There is also pressure to decrease the overall power consumption while remaining in the same physical size. And, everyone is “going green.”
These systems require many ASICs, DSPs and processors with multiple voltage rails — line cards with 30 to 40 rail voltages are not uncommon. In data centers, the challenge is to reduce overall power consumption by rescheduling the work flow and move jobs to under-utilized servers, thereby enabling shutdown of other servers.
To meet these demands, it is essential to know the power consumption of the end-user equipment. A properly designed digital power-management system (PMS) can provide the user with power-consumption data, thereby enabling smart energy-management decisions.
A large multi-rail power board is comprised of an isolated intermediate bus converter which converts -48 V from the backplane to an intermediate bus voltage (IBV) and is distributed around the card, typically 12 V to as low as 3.3 V. Individual point-of-load (POL) dc-dc converters step down the IBV to the required rail voltages, which range from 5 V to 0.6 V with typical currents ranging from 1 A to 120 A (Fig. 1).
The POLs can be self-contained modules or solutions comprising dc-dc controller ICs with associated Ls, Cs and MOSFETs. These rails have strict requirements for sequencing, voltage accuracy, margining and supervision.
DIGITAL POWER MANAGEMENT
Clearly, the sophistication of power management is increasing. Power-management circuitry must be robust, easy to use, and must not consume too much of the available board area. In the past, power-management (PM) functions have been realized using a plethora of ICs such as FPGAs, sequencers, supervisors, DACs and margin controllers. Newer power-management ICs combine multiple functions and can control all the rails on the board.
Fig. 2 shows an example of one channel of Linear Technology's LTC2978 digital power-management IC controlling a dc-dc converter. Such solutions may operate autonomously or communicate with a system host processor for command, control and to report telemetry. The LTC2978 combines all the required features into a single device that can be tied together with other LTC2978s via a single clock line and optional fault sharing lines to control up to 72 voltages on a single segment of an I 2C bus. Let's examine some of the key requirements of such power-management systems.
The PMBus command language was developed to address the needs of large multi-rail systems. PMBus is an open standard power-management protocol with a fully defined command language that facilitates communication with power converters, power-management devices and system host processors in a power system. In addition to a well-defined set of standard commands, PMBus-compliant devices can also implement their own proprietary commands to provide innovative value-added features.
The standardization of the majority of the commands and the data format is a great advantage to OEMs producing these boards. The protocol is implemented over the industry-standard SMBus serial interface and enables programming, control, and real-time monitoring of power conversion products.
Command language and data-format standardization allows for easy firmware development and reuse by OEMs, which results in reduced time-to-market for power-systems designers. For more information, visit http://pmbus.org.
DIGITAL PM SYSTEM REQUIREMENTS
Following are the major requirements that designers must consider when developing board-level digital power-management systems:
Certain processors demand that their I/O voltage rise before their core voltage, but certain DSPs require their core voltage to rise before their I/O. Power-down sequencing is now required. ASICs with seven voltage rails to sequence are now common. An ideal sequencer would allow arbitrary sequencing of any rail in the system and allow any rail to depend on any other rail. This can be accomplished by using one universal clock to synchronize all sequencer ICs to the same time base. Since sequencing delays are typically at the millisecond level, this clock can be low frequency and low noise, such as 100 kHz. In a multi-rail sequencer, most dependencies are established with configurable settings within the sequencer. If there is a need to establish dependencies across sequencers, a fault-sharing bus can be used between sequencers. A fault group may be the core and I/O rail of one processor or all seven rails on an ASIC. A dependency is established between these rails, such that if one of them does not come up to its full voltage during the power-up sequence, the sequence is aborted. For an example of sequencing up, down and margining, see Fig. 3.
High-speed comparators must monitor the voltage levels of each rail and take immediate protective action if a rail goes out of its specified safe limits. The host is notified that a fault has occurred via the SMBus ALERTB line and dependent rails are shut down to protect the ASIC. Achieving this requires reasonable accuracy and response times on the order of tens of microseconds. It is also useful to have variable deglitching of the overvoltage/undervoltage function to prevent false trips on noisy rails.
As voltages drop below 1.8 V, many off-the-shelf modules have trouble maintaining Vout accuracy over temperature. Absolute accuracy requirements of ±10 mV are not uncommon. It may be necessary to trim the output voltage. OEMs perform margin testing to ensure their systems function properly even if rail voltages drift.
This rail-voltage drift can be completely eliminated by externally trimming the module. The power-management IC contains a digital servo loop that measures the rail voltage and continuously trims out any inaccuracies.
The same digital servo loop described above is used to margin the rail voltages up and down during manufacturing test with one I2C command. There is one servo per channel.
Voltage and current monitoring
To achieve the desired reductions in power consumption, it is necessary to characterize the loads during all modes of operation. FPGA users now optimize their code to minimize power. Real-time telemetry makes this easy. Off-the-shelf modules do not report current or voltage.
To accurately measure currents without introducing unwanted loss, the power-management IC must have extreme accuracy and resolution. For example, a 20-A/1-V power stage might have an output inductor with a 0.5-mΩ dc resistance. To accurately measure its output power in increments of 1 W, a resolution of less than 500 µV is needed. The LTC2978 has a resolution of 15.6 µV and an accuracy of 0.25%.
Wouldn't it be great if you could immediately find out what's wrong with your 40-rail prototype board when it fails to power-up the first time? Now it's possible. Inside the PM IC is a log of all the faults that have occurred. It is a simple task for the PM IC to indicate which rail has faulted or which part has exceeded its temperature limit and shutoff.
Wouldn't it be great to be able to hook up your PC to a field return, click a button in a GUI and read a log of what happened in the last 500 ms prior to the failure? Now it's possible. The PM IC has a rolling average recorder that records peak and instantaneous values of voltages, currents and temperature. Designers will also find this useful during the prototype phase.
We have already discussed firmware and protocols that allow real-time communication, command and control, but a really good power-management IC must perform all of the functions without any intervention from a host processor. The PM IC is programmed at the factory. Then, set it and forget it.
USING THESE FEATURES WHILE KEEPING IT SIMPLE
That's where the GUI comes in (Fig. 4). A user-friendly interactive GUI allows the designer to plug a PC into his board through a tiny connector and use all these features. The power-management system can be completely programmed and controlled without having to write a single line of code.
The GUI translates commands into a configuration file that is stored in the EEPROM of the PM. An offline mode allows the user to develop a configuration file for loading into the part.
During board development, users interactively optimize their configuration. Once complete, the custom configuration file is sent to the IC manufacturer or the contract manufacturer and pre-loaded into the power-management IC.
First-pass success is assured. Digital power management adds value during four key phases of the system life cycle:
- During the design and development phase, the designer can configure the digital PM system to optimize sequencing, minimize power consumption and characterize system performance.
- Production margin testing is easier to perform than using traditional methods because the entire test can be controlled by a couple of standard commands over an I2C bus.
- Complicated FPGAs with a lot of custom code are not required.
- At system power up, the board is protected against faulty power converters because the PM IC immediately prevents the power-up of any voltages that are dependent on each other if one of them fails to start.
The PM IC provides a simple GUI that informs the assembler if any power supply fails. In the field, the power-management IC operates autonomously to provide continuous supervision and takes pre-programmed action in response to faults. The digital power-management system can also be used to send data back to the OEM about system health status to determine if repairs are needed.
If a board is returned, the fault log can be read back to determine which fault occurred, the board temperature and the time of the fault. This data can be used to quickly determine root cause, determine if the system was operated outside specified operating limits or to improve the design of future products.