In the previous article, we derived the origins of the right-half-plane-zero (RHPZ) and discovered how it could affect converter dynamics. If we know where it hides, we still need to explain how to deal with it when it comes to compensation. Compensating a converter means shaping the loop-gain ac response T(s) via a compensation network - usually an operational amplifier and a gang of RC elements - featuring a specific small-signal response G(s). Within this response, the designer will adequately place poles and zeros to locally boost the phase in the vicinity of the crossover frequency and make sure enough phase and gain margins exist in all operating conditions. The object here is where to place these poles and zeros when a vicious RHPZ plagues the design.
Compensation for a given converter starts with the small-signal transfer function, usually noted as H(s). Within this transfer function appear multiple poles, zeros, static gains, etc. The dc operating point of the converter represents an important starting point which is, most of the time, required to compute the position of the aforementioned poles and zeros. With a boost converter operated in continuous conduction mode (CCM) and implementing voltage-mode control, the dc transfer function M when neglecting ohmic losses, is:
Where D represents the duty cycle in Eq. 1: Equations
The CCM boost transfer function appears in numerous text books and Ref.  that compiled and documented several other topologies in both voltage- and current-mode controls. The control-to-output transfer function of the CCM boost converter operating in voltage mode is:
By control-to-output, we mean how the ac voltage present on the error amplifier output goes through the Pulse Width Modulator (PWM) and drives the boost converter output voltage. Eq. 3 indicates the presence of two zeros, one of them being our RHPZ (ωz2) plus a double pole located at ω0, affected by a quality coefficient Q. The definitions of these elements are:
Where rCf represents the output capacitor C Equivalent Series Resistor (ESR), Vin and Vout are respectively the input and output voltages, Vpeak is the PWM sawtooth amplitude, L is the boost-converter inductor affected by rLf, its series resistance, D is the converter duty cycle and Q is the quality coefficient linked to the double pole.
To illustrate the boost-converter ac response, we will take the example of a simple 60-W dc-dc converter elevating a 12-V battery voltage to a 19-V level, as in a notebook application powered from a car battery. Its specifications are:
Vin,max = 15 V
Vin,min = 11.5 V
Vout = 19 V
Iout = 3 A
R = 19/3 = 6.33 Ω
Phase margin at crossover is greater or equal to 60°, worst case.
The calculation steps using Ref.  software give us the following:
Fsw = 100 kHz
Vpeak = 2 V
L = 50 µH, rLf = 10 mΩ
C = 1000 µF, rCf = 20 mΩ
From these values, we first evaluate the operating duty cycle at the lowest input voltage thanks to Eq. 2:
Then we can proceed with the poles/zeros positions as defined by Eq. 4 through 8:
These results indicate the presence of a double pole placed at 430 Hz and affected by a 17.6-dB quality coefficient. This resonant frequency will move in relationship to the input voltage as it affects the duty cycle. The worst case occurs at minimum input voltage and full load.
However, once the compensation circuit is calculated, it is the designer's duty to make sure that the phase and gain margins do not degrade over the whole input-voltage and load ranges. Also, as parasitic elements are involved, their impact on the final loop gain must also be carefully evaluated.
Once we have the numerical results, we have several choices to plot the CCM boost converter Bode response. The first one consists in using a scientific software such as Mathcad®, which can directly handle magnitudes and imaginary notation via dedicated functions. This is the simplest and fastest approach. Unfortunately, for people without this software, we offer something simpler. For instance, directly extracting the magnitude and argument of Eq. 3 via the poles and zeros position is a possible solution that can be easily used with Excel® for instance. Capitalizing on this remark, the magnitude and argument of H(s) appear through Equations 15 and 16.
Once these equations are entered into the calculation tool of your choice, the complete Bode diagram can be unveiled as shown in Fig.1.
We are now to the point where you need to select the crossover frequency. The crossover frequency of a CCM boost converter is limited in the upper range by the lowest RHPZ position. We need to limit the duty cycle slew-rate by selecting a crossover frequency well below the worst-case RHPZ position. Experience shows that below 30% of this position gives adequate results. In our case, based on what Eq 11 tells us, the maximum crossover frequency we can reasonably obtain is:
Another consideration concerns the resonant frequency. You must always consider a crossover frequency beyond the region where the peak occurs. Otherwise the loop will not offer enough gain to damp the LC network peaking, bringing instability to your converter. A common rule is to recommend at least three times the maximum resonant frequency. In the CCM boost converter, this resonant frequency changes with the input conditions, reaching its maximum for a 15-V input level. In this case, Eq. 13 predicts a resonant point placed at 562 Hz. Therefore, the crossover frequency must stay above:
Combining Eq. 17 and 18, we will adopt a crossover point of 2 kHz. What if Eq. 18 gives an unrealistically high value? In that case, you would still have the choice to increase the output capacitor to push the resonance in a lower frequency region. Nevertheless, you must still make sure that the selected crossover frequency and the available capacitor lead to a theoretical undershoot compatible with your specification. Otherwise, another calculation iteration is necessary.
Now that we have selected a crossover frequency, you can either read the graph or use the magnitude/phase equations to extract the magnitude and the phase rotation at 2 kHz for a maximum load and an 11-V input voltage. We obtain:
COMPENSATING THE CONVERTER
The loop-stability exercise consists in shaping the compensator G(s) to provide a gain at 2 kHz that compensates the gain deficiency (or excess) extracted at the crossover frequency such that |H(fc)G(fc)|=1. In our example, we must provide a 1.77-dB gain when the frequency reaches 2 kHz. For the phase, it is a bit different. You need to provide a certain amount of excess phase at the crossover frequency to obtain the required phase margin, PM. If we look for a 60° phase margin, this so-called boost is calculated according to Eq. 21.
The phase boost is obtained by placing poles and zeros at proper places. For a boost converter operated in CCM and a needed phase boost greater than 90°, you must use a type 3 compensator. Such an amplifier appears in Fig. 2, together with the boost-power-stage configuration. Note that the lower-side resistor only plays a role in dc but is excluded in ac, given the presence of the virtual ground at the inverting pin: it has no effect on the crossover frequency.
How do we adjust the elements to provide the necessary gain and determine where to place the poles and zeros? If the k factor works reasonably well for a first-order converter (Fig. 3), it often leads to conditional stability in the case of a CCM converter featuring a resonant double pole. This is because the method solely focuses on the crossover region and not what happened before or beyond. For this reason, manual placement is the preferred way of compensating when complex Bode plots are in play. Before we present the method, we first need to introduce the transfer function of the type 3 amplifier. It is illustrated in Eq. 22.
It brings a pole at the origin, a double zero and a double pole. The pole placed at the origin is found on the vast majority of compensators. It is there to provide high gain in the dc region. This high dc gain reduces the output impedance, and improves static error and input rejection. This origin pole naturally rotates the phase by -90° (π/2), to which you must add the -180° inversion brought by the op amp (-π). Capitalizing on these remarks, the total argument of the type 3 arrangement appears as described by Eq. 23.
The most hurting contributor in the CCM boost-converter transfer function is the double pole located at the resonant frequency. One possible solution is to place in G a double zero right at this location. In some converters, it is also interesting to split these zeros, one placed at the resonant frequency and the second slightly below it, to increase the phase margin in the discontinuous conduction mode (DCM).
If the ESR zero occurs before the crossover frequency, we place a pole right at its location to force the gain decrease. The second pole will be placed at half of the switching frequency to make sure enough gain margin exists as the phase margin vanishes to 0°. In our case, the ESR zero occurs after the crossover frequency, but not too far away from it. To show the impact of this first pole position in the compensator, there are two possible strategies explained below:
A double zero, fz1 and fz2, is placed at the lowest resonant frequency, i.e. 430 Hz.
A first pole, fp1, is placed right at the ESR zero occurrence, 7.9 kHz. The purpose of this pole is to force a -1 slope despite the presence of the boost-converter resonant pole cancelled by the double zero.
A second pole, fp2, will be placed at half of the switching frequency (50 kHz) to ensure a proper gain roll off as the phase rotation further degrades. This pole gives the necessary gain margin we need (at least 10 to 15 dB).
Once all locations are known, resistor R2 from Eq. 22 is extracted to provide the proper gain compensation at fc. Ref.  details all the steps to carry these calculations.
Given the selection of the poles/zeros affecting G(s), we will evaluate the loop, T(s), resulting phase margin and see if it complies with our specification.
A double zero, fz1 and fz2, is placed below the lowest resonant frequency, e.g. 300 Hz.
A first pole, fp1, is now computed to provide the required phase margin, i.e. 60°.
A second pole, fp2, will be placed at half of the switching frequency (50 kHz) to ensure a proper gain roll off as the phase rotation further degrades.
Once all locations are known, resistor R2 from Eq. 22 is calculated to provide the proper gain compensation at fc.
When H(s) and G(s) are combined together, we observe the total loop noted T(s). The loop-phase margin, PM, after compensation is evaluated as the distance of the total phase rotation at fc i.e. arg T(fc) and the -360° limit. It can be expressed mathematically as:
Strategy 1 applied to Eq. 23 gives us a total phase rotation for the compensator, G, of -130° at 2-kHz. From Eq. 24, it leads to a final loop-phase margin of 50° at an 11.5-V input voltage, increasing to 56° when the boost converter is supplied from 15 V.
For strategy 2, we will fix the double zero to 300 Hz and adjust the position of the first pole to cope with our 60° phase-margin requirement. We know from Eq. 21 that if the compensator two zeros and the second pole are fixed, the first pole can be placed to offer the required boost of 149°. Eq. 23 includes the origin pole rotation plus the op amp phase reversal.
However, the real boost brought by the compensator G is calculated as the phase-bump amplitude above the -270° or -3π/2 limit (Fig. 3). Thus, from Eq. 23 we can extract the contribution of the first pole, fp1, by removing the -3π/2 term. Therefore, we have:
The pole position is now easily derived and follows Eq. 26.
Using this second strategy, we confirm that our phase margin is 60° for 11 V and if we compute it at 15 V, we now have 66°, above the specification target. Both compensation options 1 and 2 appear as subscripts on their respective curves in Fig. 3.
If Strategy 2 offers a more comfortable phase margin than Strategy 1, please note the gain reduction in the low-frequency region. This is the typical effect of moving the zeros farther down the frequency axis: you gain in phase margin but it will naturally affect the transient response by slowing down the system. Note that both gain curves give exactly ≈1.8 dB at 2 kHz, compensating the gain deficiency of the power stage.
Once the compensator response is shaped according to your needs, you can now combine it with the boost-converter frequency response and obtain the open-loop Bode plot we are looking for in Fig. 4. Both strategies exhibit a crossover frequency exactly of 2 kHz, together with the phase margins we predicted.
Again, Strategy 1 gives a larger low-frequency gain but gives a phase margin below 60°. Strategy 2 improves the phase margin but slightly lowers the gain in the low-frequency region.
The calculations we have made are related to the typical ESR value of the output capacitor. As everyone knows, this ESR varies from lots to lots but also in temperature. The manufacturer gives some indications of the minimum and maximum ESR.
It is important to perform the stability analysis with the ESR variations fully accounted for. In the table, we assume three different temperatures leading to three different ESR values. Then, thanks to the automated spreadsheet, we have entered these ESR values and collected the resulting phase margins depending on the two selected strategies:
As you can see, Strategy 1 fails to offer the minimum acceptable phase margin at high temperature: we are below 45°. It does not say that the circuit will fail in production, but you have a design that can potentially be marginally stable. This kind of situation is not recommended for high-volume productions. On the contrary, Strategy 2 offers enough margin, even at high temperature, where we are still above 50°.
The ideal study includes the operation of the boost converter when operated in light-load conditions. Unfortunately, the converter will change its mode, transitioning from CCM to DCM. It can be shown that the transition occurs when the load reaches its critical point:
It corresponds to a load of 69 Ω at an 11.5-V input voltage (5.2 W) or 76 Ω at a 15-V level (4.7 W). This is where the analytical analysis finds its limit: the transfer functions, both in ac and dc, change in DCM and all the equations above must be updated. Not a herculean labor, of course, but it clearly complicates and lengthens the stability analysis.
This is where an auto-toggling SPICE model would be of great help. Furthermore, it could help us predict the transient response in relationship to a set of operating conditions applied to the selected strategy.
We will see in an upcoming article that an average simulation using SPICE can help to alleviate this problem by simplifying the stability study.
C. Basso, “Switch Mode Power Supplies: SPICE Simulations and Practical Designs”, McGraw-Hill, 2008
Power 4-5-6, http://www.ridleyengineering.com
D. Venable, “The k-factor: a new mathematical tool for stability analysis and synthesis”, proceedings of Powercon 10, 1983, pp. 1-12