Power Electronics

SPICE3 Enables Accurate Modeling of Complex ICs

The capabilities of SPICE3 permit the simulation of circuits incorporating the latest ICs by way of special algorithms and modeling techniques.

Today, many analog IC manufacturers provide software models in SPICE format. With an enlarging community using electronic design automation (EDA), it's become a prominent challenge to provide SPICE users with sophisticated IC models. We will explore a few SPICE modeling basics that tie into more sophisticated modeling techniques, and provide three complex modeling examples of real-world ICs used in power design. This will provide insight into SPICE3's accommodation of tough modeling scenarios. It also will provide experience in using sophisticated IC SPICE models in analog designs.

SPICE3 Versus SPICE2

During the evolution of SPICE3 in the 1990s through today, better capability was engineered from its SPICE2 predecessor. This was done in part to enable greater accuracy with modeling primitives, which are ultimately used for the modeling of complex components.

Though diodes, comparators and amplifiers are widely used in behavioral models for constructing ICs, SPICE2 is quite limited in this area. SPICE2 only has diode and gain elements available as intrinsic building blocks. SPICE3 provides many other choices. Even SPICE3's diode function is improved through the use of a small emission coefficient (N), which scales its I-V curve alongside setting the diode temperature to 27°C. SPICE2 doesn't allow separate temperatures for individual parts.

Another nice trick with SPICE3 is if you reduce N by a factor of 1000, the diode forms an interesting macro model and looks like a very sharp switch, which switches on around 1 mV. Albeit, when reverse-biased, the diode's temperature coefficient of current is too large, so this model fails for virtually any deviation in circuit temperature. Looking further, limiters inside SPICE3 are modeled as high-gain amplifiers that switch from VLO to VHI when the input exceeds VLIMIT. The number of dc iterations to converge and the existence of derivatives before and after limiting gauge the quality of the model.

SPICE3's Comparator Model

Generally, it's disadvantageous to get initially involved in constructing a detailed model. Instead, behavioral elements are used to model core IC functions, with more detailed design added to accommodate second-order effects.

Following are two methods for modeling a comparator. Fig. 1 shows a diode-based model. With N=0.001, the accuracy is very good. Note that accuracy will suffer if SPICE2 compatibility is required.

Historically, sigmoid functions found their way into SPICE models as a result of their use in neural networks. The sigmoid equation shown in Fig. 2 has the property of being continuously differentiable, although there are practical numerical limitations. For this example, the transition is softer than the diode limiter and derivatives go to zero for a smaller range of the input function.

A closely related problem to comparators is an amplifier with limits. As the signal progresses through a cascade of amplifiers, the simulator is forced to find a tiny window of linear gain. The presence of derivatives over a wide overload range is critical to convergence. The sigmoid function must be integrated before it can be used in an amplifier. The amplifier with limits in Fig. 3 was constructed using two sigmoid integral functions, one for the positive limit and the other for the negative limit. The two subcircuits at the top right of Fig. 3 are used to construct a linear output window between 80 V and 100 V.

These and other techniques highlighted in the following examples are needed to accurately model complex ICs.

HID Lamp Controller IC

Most of the logic in the UCC2305 high-intensity discharge (HID) lamp controller IC normally requires many minutes of time to be simulated. However, an average model of the switching regulator within the IC SPICE model (Click to view Fig. 4) is constructed to dramatically lessen the run time (about 55 times faster). For switch-level component stress analysis and design validation, the switching model should be run for several cycles at each operating point to be investigated.

The SEPIC converter is actually a compound boost-buck converter. It can be modeled in continuous-conduction mode using two average voltage-mode PWM circuits. The advantage of this model lies in its computational efficiency.

Much of the UCC2305 circuitry deals with thermal time constants that require a simulation time of 100 sec or more. But again, to test these features, the average model is mandatory. A unique VSECTOL convergence option is selected to enable accurate-time step control during this process.

The plasma in a HID lamp driven by the UCC2305 forms in several seconds. The thermal model submits radiation loss from the lamp and is modeled as a “thick” spectrum. Electrode emission loss of the lamp also must be modeled as well as conductivity versus temperature, power control, warm-up logic, undervoltage lockout and the ac switching feature.

One-Cycle Control PFC IC

The gain of the integrator within the IR1150 IC (click to view Fig. 5) is an important factor in making the load appear resistive as the input voltage varies. Integrator gain is not discussed in the data sheet or application note. A simulation was performed to find out how the gain varies with frequency to maintain the proper power-factor-correction (PFC) behavior. Two voltages, 150 V and 75 V, were used to find out the required gain. The relationships are shown in the table.

The circuit used to test the PFC stage of the IR1150 is essentially the one described in its application note, except that a 2-µH boost inductor was selected to make some of the earlier runs have lower ripple current. In the simulation, a 1.5-µH inductor in parallel with a 50-Ω resistor was used to simulate a ferrite bead in series with the output. Not only does the EMI signature improve but so does simulator convergence. The EMI filter might need revising, using two sections to meet the conducted emissions requirement. Alternatively, the frequency could be modulated by connecting a resistor between the rectified ac and the FREQ pin. Properly adjusting the steady-state COMP pin voltage enables shorter simulation time.

Table. IR1150 IC integrator gain versus frequency for power-factor-correction operation.
Gain Frequency
2.4 × 10-6 49.7 kHz
4.65 × 10-6 95 kHz
1.075 × 10-5 210 kHz

PWM Controller IC

In simulations of UCC2891 current-mode active-clamp PWM controller IC (click to view Fig. 6), the internal oscillator is modeled separately. Ideal current pulses are used to simulate the gate-drive signals, and are thus reflected back to VDD. However, this idealization still provides correct peak current, rise/fall times and drive impedance.

In the UCC2891 test circuit (click for PDF), second-order effects were estimated for the power transformer, filter inductor, magnetic di/dt coupling and filter capacitors in order to see parasitic ringing. This ringing may need to be filtered to comply with EMI specifications. Additionally, the measurement of this parameter in the test circuit is affected by scope bandwidth.

The causes of high-frequency output ripple include: the combination of the ceramic capacitor and electrolytic capacitor lead-inductance, and the filter-inductor parallel capacitance; magnetic coupling between the switching loop and filter loop; and electrostatic coupling by the transformer parasitic capacitance.

Input ground and output ground are assumed connected together externally. Your lab power supplies will do this via their own EMI filters and the application will probably connect them via the safety ground (as simulated by L2 in the SPICE test circuit). Moreover, there will be some parasitic capacitance connecting them on the printed wiring board (simulated by C3 in the SPICE test circuit). The noise current in the parasitic capacitance has high amplitude and is very broad in bandwidth, hence the need for better EMI filtering.

The TLV431A Zener model that was used for the simulation requires the SPICE RSHUNT option to converge. Time step is under the control of a special VSECTOL convergence option in the simulator. The initial operating point is automatically calculated using another special convergence option, ICSTEP.

For successful modeling of today's complex ICs, special convergence options must be built into a high-end SPICE3 simulator's kernel. Other aids include general feedback theorem (GFT) injection models for preserving closed-loop dc bias while taking open-loop measurements, ultrafast average modeling technology and modeling savvy. As with any design-automation tool, simulation will ultimately achieve a more production-ready system by tackling worst-case design and test scenarios before going to pc-board fabrication.

Information on GFT injection models are available at http://intusoft.com/gft.htm.

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