A block diagram of the target design is shown in *Fig. 6*. The observed input and output voltage can be filtered using the Kalman technique, but the trick here is to avoid measuring the noisiest variable altogether. That saves a sense resistor and the signal conditioning circuits surrounding the current measurement. Moreover, the analog compensation components are not needed — they are folded into the DSP software. However, a simple resistor divider signal-conditioning network must be added for each of the two voltage measurements. These networks bring the signal range down to the A/D converter measurement range. The relatively heavy signal filtering in the PWM input and output filter acts as the DSP anti-aliasing filter so that further analog noise filters are unnecessary. The controller itself can use average current or peak current control, borrowing from the ISSPICE4 models used to make average model PWM controllers.

Note that the dc component of current is based on the plant series resistance being the same as the actual sum of inductor resistance and switch resistance, while the high frequency component depends on accurate modeling of the filter inductance. The effect of errors in modeling on stability margins must be considered.

### TARGET DESIGN

The design of a buck regulator will be analyzed. The target design operates in continuous conduction mode (CCM) with common input and output grounds. This might represent an auxiliary 5-V regulator where an off-line SMPS provides the 12-V source. The DSP output directly controls duty ratio. The duty ratio is computed based on voltage measurements made near the beginning of a PWM cycle, the average current from the plant model and the estimated charging current. Then, the continuous time model is transformed to a z-transform-based model. Finally, the z-transform equations are rearranged into the familiar infinite impulse response (IIR) DSP equations.

Because it is not altogether obvious this approach will work, the following considerations will be checked:

- Is the accuracy of the ISSPICE4 I
_{AVG}high enough to calculate cycle-by-cycle peak current? - What happens if the model and hardware parameter values differ?
- Is the voltage-matching loop stable?

The design shown in *Fig. 7* was used to investigate these considerations. For this investigation, the plant model is in the analog domain.

Notice the input and output filters are real-world designs that filter the switch-mode noise to reasonable levels. The input passes the MIL-STD-462D requirements, while the RMS output ripple is 2.5 mV_{RMS}.

The zero order hold is used to transform the average PWM model into the sample data domain. The behavioral equation in B1 (Fig. 7) is based on the calculation in *Fig. 8*. This equation solves for the duty ratio in a peak current-mode controller. Many possible formulations of this equation exist, depending on how the average switched inductor current is defined. Taking the average as the value between the beginning of the PWM cycle and the peak current switch point yields a simple equation. Conversely, if I _{AVG} is defined as the average between the previous PWM switch point and the next PWM switch point, then a quadratic expression is encountered that could fail if the square root argument is negative, not to mention the possible oscillation between the two solutions. In any event, the various methods of defining I_{AVG} result in the same steady-state solution. The definition adopted here and the resulting model have good agreement when comparing the IsSPICE4 average model and switched circuit. Where:

V_{C} = control voltage

R_{B} = burden (sense) resistor

D = duty ratio

L = inductance of the switched inductor

F = switching frequency.

Answer to consideration 1: A transient simulation was run with the same plant and circuit parameters; the RMS error in estimating I_{AVG} over the entire simulation was 2.6% with the EMI noise injection turned off.

Answer to consideration 2: Bode plots for the three control loop cut points taken at V1, V7 and V8 show the typical stability margins in *Figs. 9, 10* and *11*. These margins remain acceptable if the circuit inductor is varied from 25 µHy to 125 µHy with the plant model inductor reaming at 75 µHy. The loop cut taken at V1 is not available in hardware, because it's part of the mathematical reconstruction of the current-mode control system. This is the innermost loop, and it is a powerful tool that can be used to design a stable input filter.

Answer to consideration 3: Fig. 11 shows stability in the voltage matching loop.

The remaining part of the model is the computational delay. The easiest thing to do is start the PWM cycle after making the duty ratio calculation and insert a delay line in the model to represent the computational delay time. However, for steady-state operation, the duty cycle may exceed the time required to make the calculation. To get around this, the A/D can be sampled before starting the PWM. This also removes switching noise from the A/D input. Applying the PWM commands immediately is best if the digital comparator use is greater than or equal to logic.

*Fig. 12* shows simulation results that compare linear and digital performance. *Fig. 13* validates the plant model performance.

### CONVERTING SPICE NETLIST TO A DSP PROGRAM

Most digital control systems use a digital controller to shape the feedback response based on a single input and output. The previously described direct programming method works in these situations. Unfortunately, there are a number of interwoven control loops in this proposed solution. Both duty ratio and the plant model for output voltage appear as input and outputs.

The way SPICE handles the problem is to construct a matrix to solve the simultaneous equations. For linear equations, the solution requires no iterations; however, for nonlinear equations, the solution is iterated with the new computed operating points — along with the partial derivatives that are inserted back into the matrix.

A Microchip SMPS buck development board with a DSPIC30F2020_SDIP300 DSP [5] was used to validate this design concept. First, the filter capacitor was changed from a conventional aluminum electrolytic capacitor to an aluminum-polymer capacitor to reduce ESR. The filter inductor was replaced with a higher current carrying part. Later, a Schottky diode was added across the upper switch, a ferrite bead was placed in series with the upper and lower switches, and an input noise filter was added.

Three different algorithms were coded. First a proportional-integral-derivative (PID) controller was implemented. Although this is what the board started with, the aluminum-polymer filter capacitor changed the problem. Then, the current sense built into the board was used to make a dual-loop controller, current inner loop and PI outer loop control. That's more in line with current SMPS technology. Next, a new algorithm was coded using a plant model to extract current as a hidden variable without needing to measure current. As part of the hardware testing, the sine-cosine generator and transfer function analyzer were coded to make gain and phase measurements. A 50-Ω pulsed load is built into the evaluation board. Several interesting properties of the board and microcontroller include:

- Independent PWM frequency and A/D interrupt frequency
- A/D trigger control anywhere in the PWM cycle
- Synchronous buck topology enables active loading.

The independent power conversion and data sample frequency allow optimization of power handling without being compromised by computational time requirements. There's no real cliff to drop off of as the computational delay grows; the control performance degrades gradually. The analog controller performance is locked to the switching frequency and will consistently provide higher bandwidth than a DSP solution.

A/D triggers can be used to sample the output voltage when switching noise is minimal. Synchronous power conversions results in negative current, which can't be detected using the built-in high-side sense circuit. That makes the current control using the plant model hidden variable even more attractive. Control system designers are averse to using derivative feedback because the noise is amplified, reducing the controllers dynamic range. In the worst case, the noise reduces gain so severely that low-frequency, large-scale oscillations occur. Designers usually use a derivative measuring device such as a tachometer or rate gyro in mechanical systems. The analog of that is the inductor current in an SMPS. Inner-loop current control also reduces input variation sensitivity.

The Microchip evaluation board can be run in a synchronous switching mode. In this mode, inductor current is continuous, and the converter also can operate in boost mode to deliver power back into the load, using the same control loop dynamics. One of the converters can be used to load the other in order to simulate a load. An active load was made using a resistor connected between the two converters. Then, one of the analog inputs was used to control the voltage difference between the source and load. The sense resistor was selected to be 1 Ω, a bit larger than needed to reduce the interaction of the two control loops. Controlling the difference between the two “outputs” results in a constant current load, while controlling the voltage of the second converter results in a resistive load simulation.

The test data in *Fig. 14* shows how the two control loops respond to a 1-A load step. Both have the same initial peak disturbance, but the control loop using current feedback damps the ringing. Pk-pk duty ratio noise is 7% and 9% for the PID and current loop, respectively. The PID loop was run at Fs = 100 kHz and the current loop Fs was 78 kHz to accommodate the longer computational time. The plant model added about 3 µsec to the computational time.

Noise basically is caused by errors in measuring the output voltage. These errors can be the result of various random noise sources, systematic interference from switching signals and A/D quantizing effects. Quantizing error dominates this application. Quantizing error causes the measured output to jump between levels by a least significant bit (LSB) to achieve the average of the commanded signal. It resembles a mini SMPS within the main switching loop. The pk-pk error is amplified by the system gain from output to the duty ratio. Being aggressive with compensation (maximizing bandwidth) causes the gain to peak when the phase crosses zero. For the PID case, the gain is about 9, resulting in noise that is 9 × LSB = 90 m or 9% duty ratio noise (measured 7%). It is about the same using current feedback. However, combining the measured value of output voltage with the predicted value in the plant model reduces noise. For the example, the loop bandwidth was increased with respect to the switching frequency to achieve similar peak switching response. So, the noise gain from the Kalman technique offsets the lower sampling frequency.

The PID solution is an optimal controller for 2 ^{nd} order systems when response to commanded change is desired. Yet, the SMPS problem is not concerned with response to reference voltage change. Instead, the power supply should be impervious to line and load changes. The current-mode settling time and line sensitivity are much bettercompared to a PID design. Because the system exceeds 2^{nd} order, a slightly more complex control loop compensation would provide a bit higher bandwidth. The plant model offers advantages in noise reduction and eliminates the current sense components used in a conventional SMPS. Coding DSP is extremely error-prone, even passing coding errors that appear to work. The design complexity level makes the decision to use these devices in new designs quite difficult. The engineering effort is higher than for a comparable analog design, which leads to increased risk that must be mitigated by increased testing and analysis. Exposing the DSP design to increased scrutiny through testing and simulation is necessary. *Fig.15* shows the target design with various test probes.