A growing number of electronic devices require both data connectivity and a power source to function effectively. The IEEE 802.3af standard outlines a method for delivering power and data over LAN cables using the existing Ethernet infrastructure. A key element of this standard is that the power delivery must be isolated on the user or powered device (PD) side. This isolation requires the use of an isolated power topology within the PD.
The most cost-effective power topology to provide this isolation with acceptable efficiency is the continuous-mode flyback. To implement the flyback effectively in PDs, designers must understand the basic operation of this topology and the equations needed to design the flyback transformer.
In Power-over-Ethernet (PoE) applications, the power-sourcing equipment (PSE) supplies a voltage of 36 Vdc to 57 Vdc to a PD. However, very few, if any, devices will require voltages in this range. As a result, a power supply inside the PD must convert the available power to the regulated voltage required by the electronics within the PD. The designer of the power supply for the PD must find the most cost-effective, space- and energy-efficient means of accomplishing this task.
Due to the requirement for 1500-VRMS isolation, an isolated power topology must be used. For the power levels required for the existing PoE specification (less than 13 W), the flyback converter is the simplest and least-expensive isolated topology. Traditionally, for non-PoE applications at these power levels, a discontinuous-mode flyback is generally used because it usually requires a smaller transformer. It also provides faster transient response due to a lower primary inductance, and the feedback loop is easier to stabilize than a continuous-mode flyback.
However, for PoE applications where efficiency is critical, the respective sizes of the transformer needed for the continuous and discontinuous modes are essentially the same, and the lower peak currents of the continuous flyback improve overall efficiency. Furthermore, the right half-plane zero in the continuous-mode flyback is suffciently high so as not to affect the stabilization of the feedback loop.
As a result, the vast majority of published PD power reference designs use a continuous-mode flyback topology. Reference designs from of several power IC vendors demonstrate that this topology is capable of efficiencies in excess of 90%, which is sufficient for most PoE applications.
Overview of Flyback Topology
A basic understanding of the continuous flyback topology is necessary to derive the equations for the PoE power transformer design. A simplified schematic of the flyback topology is shown in Fig. 1. The primary switch S1 is a MOSFET, and the secondary switch S2 can either be a diode or a second MOSFET operated as a high-efficiency synchronous rectifier. Regardless of the exact implementation, the flyback topology’s switching cycle has two distinct stages.
The first stage is the on-time stage, in which S1 is closed and the input is connected to the primary winding (NPRI) of the transformer for a period of time defined by tON.
During this stage, S2 is opened (representing either the turning off of the MOSFET or the reverse biasing of the diode), and the schematic reduces to the circuit in Fig. 2. In this schematic, the transformer’s primary-winding leakage inductance is shown as a separate inductor, and the resistance of S1 is shown as a resistive element, along with their respective voltage drops. When S1 is closed, current flows through the primary winding, but the change in current is limited by the primary winding’s inductance according to Faraday’s law:
where DIPRI is the change in primary-winding current (amps), VPRI is the voltage across the primary winding (volts), tON is the duration of the S1 closure and LPRI is the primary-winding inductance (microhenrys).
The changing primary current creates a magnetic field in the core of the transformer, which in turn induces a voltage across the secondary winding.
However, because the S2 is open, no current can flow and the energy created in the primary winding is stored in the magnetic field of the core. The energy stored is equal to:
And, by definition, power is simply energy divided by time: (Eq. 7)
It should be noted that, even though no current is flowing in the secondary, voltage is present (VSEC) and does create stress across S2, which is an important factor in determining the turns ratio (NPRI / NSEC):
where VS2 is the voltage across S2 (volts), VIN is the input voltage (volts) and VOUT is the output voltage (volts). Eq. 8 implies that the turns ratio must be large enough to prevent excessive stress across S2. It also should be noted that, during this time, the primary leakage inductance is storing energy, but that this energy represents a loss in the circuit, as there is no mechanism to transfer it to the secondary. During the on-time stage, the output current is supplied by the output capacitor, because no current is flowing through the transformer’s secondary winding.
During the second stage of the flyback-topology switching cycle, S1 is opened and S2 is closed. The schematic reduces to that shown in Fig. 3. The primary current is zero because S1 is closed. However, the magnetic field in the transformer cannot change instantaneously and, therefore, looks for a path to dump the stored energy. It does this by reversing the polarity on the secondary winding and sourcing current to the load. The current being delivered to the load ramps down linearly according to Faraday’s law starting from its peak value:
where is the peak secondary-winding current (amps).
The slope of the ramp is:
where N equals NSEC/NPRI.
The changing current (DISEC) reduces the flux density of the core:
Substituting in Eq. 11:
During steady-state operation, the magnitude of the decrease in the magnetic field (DB) during the off time must be equal to the magnitude of the increase during the on time. This leads to the relationship:
It is important to note that although there is no current flowing in the primary winding during the off-time stage, the primary winding does see the reflected voltage of the secondary winding (VSEC):
When S2 is turned off, the energy in the leakage inductance of the primary winding must be dumped. However, because S1 is open, there is no immediate path for current to flow, so the voltage across the leakage inductance rapidly increases until it can push current through the parasitic elements of the capacitance of the transformer primary and the output capacitance of the MOSFET. This leakage spike along with the induced voltage on the primary winding creates a voltage stress S1:
VS1 = VIN + VLK + VSEC3 (NPRI / NSEC), (Eq. 17)
And (Eq. 18)
where VLK is the voltage across the leakage inductance (volts), CPRI is the capacitance across the primary winding (Farads) andis the drain-source capacitance of the MOSFET (Farads).
Eq. 17 implies that the turns ratio should be small enough to prevent excessive stress on S1. In addition to stressing S1, which often requires extra snubbing circuitry for protection, the leakage inductance delays the transfer of power from the primary to the secondary. Therefore, minimizing leakage inductance is a key element to flyback-transformer design.
Continuous, Discontinuous Flyback Modes
Fig. 4 shows three different sets of primary and secondary waveforms. In both continuous and discontinuous modes, the initial primary current starts at zero. In Fig. 4a, during the off-time the secondary current ramps down to zero because all of the energy stored in the magnetic field during the on-time of the transformer has been delivered to the load before the start of the next cycle. This creates a period of time (tDEAD) in which no current is flowing in the transformer and the circuit is said to be in discontinuous mode. As can be seen in Fig. 4a at the start of the next cycle, the primary current again ramps up from zero.
In continuous mode, the initial primary waveform starts from zero, but during the off time, the secondary current does not deliver all of the stored energy to the load before the start of the next cycle. As a result, energy is left in the transformer’s magnetic field. At all times, current is flowing in the transformer (tDEAD = 0) and the circuit is said to be continuous. As can be seen in Fig. 4b, the primary current begins its ramp at a nonzero point, defined as:
IPRIMIN = ISECMIN3 (NSEC / NPRI), (Eq. 19)
where IPRIMIN is the minimum primary-winding current (A) and ISECMIN is the minimum secondary-winding current. It should be apparent from these waveforms that the two main factors, other than the turns ratio, that influence whether a circuit is continuous or discontinuous are the transformer primary inductance (which controls the slope of the current ramp) and the required output current (which controls how much energy is taken from the transformer). As will be seen later in the article, although it is possible to design a transformer that always operates in discontinuous mode, any continuous-mode transformer will eventually go discontinuous as the load current is decreased below a minimum threshold IOUTMIN.
Flyback Topology Waveforms
Before starting any flyback-transformer design it is necessary to understand how the previously discussed current waveforms relate to the output current IOUT,RMS(which affects heating in the transformer) and IPRIPK (which affects transformer saturation). Once this is understood, it is easy to derive the required design parameters. Figs. 5 and 6 show a close-up of the primary and secondary waveforms for a discontinuous- and continuous-mode flyback transformer. Note that the dc value of any waveform is simply the average value of the waveform over the fundamental period of the switching cycle (T) and that, by definition, the root-mean-square (rms) current is:
where T1 and T2 define the start and stop times of the period, respectively. Evaluating the integral and calculating teh average (dc) value leads to the following equations:
and continuous mode:
and continuous mode:
It should be clear that the boundary between continuous mode and discontinuous mode, also known as the critical-conduction mode (CCM), occurs when the secondary of the transformer delivers all of the stored energy at the end of the switching period T (as shown at the bottom of Fig. 4c). In this case, tDEAD is equal to zero:
TON + TOFF = T. Or, using Eq. 1, TOFF = (1 – D) 3 T.
If all of the stored energy is delivered to the output (minus system losses or efficiency), then:
where h equals efficiency.
POUT = IOUT3 (VOUT + VS2).
Simplifying gives: (Eq. 31)
For any given application, there is a primary-winding inductance that will dictate if the transformer operation is discontinuous across the full output-current range (LPRI < LCCM), or if it is in discontinuous mode below some minimum output current, and in continuous mode (LPRI > LCCM) above this current.
Eq. 31 defines inductance at the CCM for a given duty cycle. Typically, a duty cycle is selected and the turns ratio is then calculated to produce the desired duty cycle. The turns ratio will affect the stresses on the primary and secondary switches. As shown in Eqs. 8 and 17, the turns ratio must be large enough to minimize stress on the S2 and small enough to minimize stress on the S1. This bounds the absolute maximum and minimum turns ratio.
Once the turns ratio is selected, the value of the primary inductance (LPRI) is chosen to ensure that the transformer always runs in discontinuous mode up to the maximum output (IOUTMAX) or that it runs in continuous mode down to some minimum output level (IOUTMIN). As a result, Eq. 31 can be redefined as follows:
For discontinuous mode:
For continuous mode:
It should be noted that in continuous mode, because there is no dead time, the turns ratio alone for a given input and output voltage sets the duty cycle. However, for discontinuous mode operation, the existence of the dead time means that duty cycle is affected by the turns ratio and the primary inductance.
The easiest way to illustrate the use of the previous equation is to run through a quick design example that will also illustrate the differences between the continuous mode and discontinuous mode flybacks.
For simplicity, the equations will be designed for a PoE input (33 V to 57 V) with a single output (5 V/12 W) switching at 200 kHz. It will be assumed that the primary switch voltage drop (VS1) is 0.4 V, the secondary switch voltage drop (VS2) is 0.3 V and that the overall efficiency is 90%. Multiple output applications can use the same design procedure by selecting one of the outputs as the master and combining all of the output power onto this one output. This will allow the selection of the duty cycle, primary inductance, turns ratio, primary peak and root-mean-square (rms) currents. The only difference is in calculating the rms currents on each of the secondary windings. This requires careful attention to the secondary waveforms of each output.
Select a maximum duty cycle, calculate the resultant turns ratio and analyze the voltage stresses on the primary and secondary switches. If the stresses are too high, the duty cycle can be adjusted and/or the switch ratings can be increased.
Select a duty cycle maximum equal to 45%.
Calculate the turns ratio using Eq. 15 and assuming that tDEAD=0:
Select the actual turns ratio of NPRI/NSEC = 5.
Recalculate the actual duty cycles based on actual turns using Eq. 15:
Analyze the voltage stresses using Eqs. 8 and 17:
Assuming VLK=0.33VIN: VS1=1.3357+5.335=100 V.
Calculate the primary inductance at the boundary condition and select inductance for application. If discontinuous, recalculate the actual duty cycles.
Calculate the boundary inductance for discontinuous mode (DCM) using Eq. 33:
Calculate the boundary inductance for continuous mode (CM) using Eq. 34. Assuming that IOUTMIN = 0.5 3 IOUTMAX:
Select the inductance for application with a 5% margin:
For DCM operation, the inductance chosen will affect the dead time (tDEAD) and, therefore, the actual duty cycles.
Recalculate the DCM duty cycle using Eq. 31:
Calculate the off time (DOFF= tOFF/T) from Eq. 15:
Calculate the worst-case DI, IPK and IRMS for each winding.
Calculate the secondary ripple current from Eq. 11.
Calculate the secondary peak currents (IPKsec) using Eq. 28.
For DCM: IPKsec =
Calculate the secondary rms currents (IRMSSEC)using Eqs. 22 and 24.
Calculate the primary peak current (IPRIPK) using Eq. 9.
Calculate the primary rms current (IRMSPRI) using Eqs. 21 and 23.
Note: For CM,
Typically, it is not the design of the transformer that leads to a nonoptimized flyback design, but rather a failure to calculate the design inputs correctly. Once the primary inductance, primary peak current, turns ratio and primary and secondary rms currents are known, the transformer can be designed following any standard procedure. Typically, a core size is selected and the number of primary turns (to achieve the inductance and peak current without saturating) is calculated.