New processors for notebook computers demand more from their power supplies: higher currents, faster response to load steps and faster output voltage changes in response to an updated voltage-identification (VID) code. Reusing an existing power-supply design in a new system would be preferable if it could meet the latest load-step specifications, offer low ripple and guarantee high efficiency in all operating modes, especially during standby.
Unfortunately, older controllers can't provide fast load steps directly through existing output inductors, so they need additional bulk capacitors to smooth transients. The space available for the new power-supply design is the same as that available for the older design, however, so additional capacitors won't fit. What are the alternatives?
For most notebook applications, a 2-phase design keeps inductor currents at or below 20 A per phase, gives the fastest response to load steps and yields the lowest cost. The switching frequency must be set high enough to respond to load transients at the required slew rate. The RDSON of the MOSFETs must be kept low to minimize high-frequency switching losses, and the bandwidth of the controller's feedback loops must be high enough to guarantee fast response.
However, older controllers have limited bandwidth. Raising the switching frequency doesn't help, because the low bandwidth limits the loop response. The inductors can't supply large current steps, so more bulk capacitors will be needed. This is expensive in cost and size, and limits the response time for on-the-fly output voltage steps.
New multiphase synchronous buck controllers solve these problems. Their stable, high-speed feedback loops permit smaller designs at lower cost. Some controllers also offer single-phase operation at lower switching frequencies, greatly improving efficiency for low or intermittent current demands.
Properly compensated, a high-bandwidth controller handles maximum load steps without oscillation. The controller provides more current, faster from the inductors, so less charge is required from the bulk capacitors. New controllers respond quickly to current transients, simultaneously turning on multiple phases, increasing the available load current without additional bulk capacitance. The controller handles the big load steps, making inductor, capacitor and MOSFET choices fairly straightforward.
A switching frequency (FSW) of a few hundred kilohertz per phase provides a good tradeoff between switching losses, ripple and output filter size, though many controllers will go higher. The value of the inductor used in the output filter depends on ripple requirements, not output voltage.
where VVID is the programmed output voltage, R0 is the load resistance, DMIN is the minimum duty cycle and VRIPPLE is the allowed ripple voltage due to inductor ripple current. The peak-to-peak ripple current in the inductor should be less than half of its maximum dc current. An 8-A ripple current gives a 20-mVPK-PK ripple voltage with a 2.5-mΩ load. For a 2-phase supply, a VVID output voltage of 1.1150 V and FSW = 280 kHz, Eq. 2 gives L ≥ 423 nH.
The inductor should not saturate at the per-phase peak current and should handle the power dissipation from core loss and average winding current. Using the smallest possible inductor reduces the number of output capacitors. The dc resistance (DCR) of the inductor affects current sensing in many controller designs, with its value providing a tradeoff between power loss and measurement accuracy.
Minimizing Output CapacitanceCeramic and bulk capacitors perform different jobs at the output of a switching regulator. Ceramic capacitors take care of high-frequency transients at the CPU. Placing them inside the CPU socket provides best transient suppression, but this limits the number of capacitors that will fit. Additional capacitors, if needed, must be placed alongside the socket.
The worst-case transient is usually a maximum load step out of deep sleep. The switch's on-time, maximum output current step and maximum output slew rate all determine the required output filter at the CPU power pins. For most notebook applications, output capacitance should be at least 300 µF, which can be obtained by using 32 0805-sized 10-µF ceramic capacitors.
Variations in pc-board parasitics may change the amount of capacitance needed. Aside from their high cost and large size, simply throwing a lot of bulk capacitance at low-frequency output filtering won't work. On-the-fly voltage changes impose an upper limit — the supply must make a voltage step and settle with a specified error band within a given time. The output needs a minimum capacitance for smooth load release with the maximum load step ΔIO and the maximum allowable overshoot — that's the lower limit.
With a maximum allowable overshoot VOSMAX, the load release voltage is:
ΔVO = ΔIO × RO + VOSMAX.
These equations define the limits on bulk capacitance (CX):
where CZ is the total output ceramic capacitance, VV and tV are the VID-on-the-fly output voltage change and response time, n is the number of phases, and K = -1n(VERR/VV). In this last term, VERR represents the settling error.
To meet the equations, the effective series resistance (ESR) of the bulk capacitors should be less than twice the droop resistance (RO). If the equations give a CXMIN that's larger than the CXMAX, either the inductor can be reduced or more phases can be added to meet the VVID step requirement. Maintaining the same output ripple with a smaller inductor requires a higher switching frequency.
As an example, with CZ = 320 µF, a 22-µs VID on-the-fly 220-mV step (tV and VV), a 27-mV overshoot limit and a 10-mV settling error, the bulk capacitors should be in the 1.1-mF to 2.1-mF range. Four 330-µF aluminum-poly capacitors, each with typical 6-mΩ ESR, gives a total of 1.32 mF total with 1.5-mΩ ESR. The effective series inductance (ESL) of the bulk capacitors should be low enough to limit high-frequency ringing during a load step. ESL ≤ CZ × RO2 × Q2, with Q2 limited to 2 for a critically damped system.
If the ESL of the bulk capacitors is too large, either the number of ceramic capacitors can be increased or lower ESL bulk capacitors can be used.
MOS power devices in buck supplies need low RDSON to minimize conduction losses and power dissipation. They also need low input capacitance to minimize turn-on time. Faster devices with lower CISS have higher RDSON, so a compromise is necessary. The gate drive is limited to 5 V by the MOSFET driver, so MOSFETs with logic-level thresholds are the only choice. Power dissipation from main and ripple currents dominates synchronous MOSFET power losses.
Synchronous MOSFETs can accidentally turn on if their reverse-transfer capacitance couples enough charge to the gate when the switch node goes high. This results in shoot-through with both main and synchronous devices on. Use a 1-to-10 or lower ratio of feedback capacitance to input capacitance in the synchronous devices to prevent it.
The turn-off time for the synchronous MOSFETs should be less than the nonoverlapping dead time of each phase's MOSFET driver. As an example, the ADP3419 MOSFET driver from Analog Devices has a 1.5-Ω output impedance and 45-ns typical dead time. Using MOSFETs with typical 1-Ω gate resistances and keeping the RC time constantly less than 45 ns gives an upper limit of 9000 pF on total gate capacitance. When using two parallel MOSFETs, the gate capacitance of each should be less than 4500 pF.
High-side MOSFETs need to handle power dissipation from conduction currents and switching losses. Switching losses come from turn-on and turn-off times, so the input capacitance of these FETs must be lower than that of the synchronous MOSFETs.
One more thing to check is the driver dissipation for each phase. The total of each driver's standby power plus the power needed to supply the gate charges should be less than the driver's dissipation limit at the highest ambient temperature. For SOIC packages operating up to 90°C pc-board temperature, 0.5 W of total dissipation gives a safe 120°C junction temperature.
Capacitor RecommendationsThe high-side MOSFET's drain current is a rough square wave with a duty ratio equal to n × V OUT/V IN and amplitude of the maximum output current times 1/n. Low-ESR input capacitors, sized for the maximum root-mean-square (RMS) current, must be used to filter ripple at the input. This RMS current is:
With a maximum duty cycle DMAX of 0.144 for minimum 8-V battery voltage, Eq. 5 gives an ICRMS that is equal to 9.05 A.
Capacitor manufacturers' current ratings may be based on only 2000 hours of life, so capacitors with ratings higher than the calculated ICRMS should be used. The input capacitor's value is determined by the acceptable amount of ripple. The capacitor's ESR and ac current must be kept low to meet system requirements.
Response to Fast Load Changes
The controller must respond to maximum load steps and load releases transparently. Older architectures with excessive turn-on delays for each phase aren't fast enough. The controller, drivers and MOSFETs also need to be fast enough to meet on-the-fly VVID change specifications.
Older single-edge designs wait until the next clock cycle to respond to load transients that occur while the controller is inactive. Clocking only one phase at a time, they force the power supply to provide current from the bulk capacitors. When they catch up, they can typically only power up one phase at a time. Newer controllers use asynchronous correction to reduce load-step response time with fewer capacitors. They can turn on all phases at once to supply CPU current demands without built-in clock delays.
Synchronous buck controllers such as the ADP3207A from Analog Devices sense sudden load changes. They restart all phases in sync with the load step, supplying maximum current without waiting. Their typical all-phase response time to a worst-case step is 1 µs or less. Extra current goes into the load, with normal multiphase operation following after the initial load-step demand is satisfied, so ripple doesn't increase.
Some controllers turn on all phases at once to handle large load steps. Most of them use a linear transfer characteristic to process load changes and control outputs. The ADP3207A on the other hand uses nonlinear gain to respond to load steps. Large signals from a maximum load step hit the high-gain part of its transfer curve to turn on all output phases. Smaller load steps at the low-gain part of the curve cause normal PWM changes to individual phases. This gives better noise immunity and low jitter, since most noise will be on the small-signal, low-gain part of the transfer curve. Controllers with a constant high gain are much more susceptible to noise.
Most mobile applications use 2-phase supplies, but these controllers can easily be configured for three phases for higher efficiency. Input current to each phase decreases with the number of phases, so battery drain is lower at any given time. The penalties are cost and space for additional components.
Fig. 1 shows an all-phases-on response to a load step. Two phases were used in this example. Mobile controllers need to operate efficiently in battery-saving low-power modes. The ADP3207A changes to a single-phase operating mode when the processor selects low power. In this mode, the switching frequency is proportional to the load current for best power efficiency. The single-phase synchronous MOSFET is controlled to prevent reverse inductor current. A circuit example appears in Fig. 2.