Power Electronics

Eco-Friendly Testing of Solar-Cells Used in Ionizing Radiation Ambient

A novel and eco-friendly approach towards preemptive testing of solar cells intended for space-borne and nuclear environments is presented. It does not require the use of isotopes and follows a traditional electrical testing suite. Further, it is an experimental evaluation and therefore is better than any model-dependent computer simulation. It also facilitates an accelerated test procedure.

Preemptive testing of solar-cells intended for use in ionizing radiation (IoR) ambient is needed to assess the extent of degradation caused in the device as a result of high energy cosmic radiations that prevail in space and/or in nuclear environment. Further, such tests are useful in pre-evaluating the robustness of the device prior to failure considerations in their applications in harsh IoR ambient. Relevant reliability issues can be profitably adopted in the design of the device towards radiation hardening (that is, for rad-hard techniques) [1-5]. Preemptive test methods can be logically designed to facilitate accelerated test methods.

Semiconductor devices in general are discrete and of large to ultra-scale microelectronics. They are tested for their “rad-hard” compliance by two methods:

  • Semiconductor studies based on appropriate device modeling under radiation dosages [5, 6] when real-life measurements of certain conditions are not feasible and/or when the measurements yield a limited-data conducive only for statistical interpretations
  • Actual use of high-energy particle sources that enable necessary fluence for irradiation [1, 4].

While the first method is very much model-dependent, the second method needs elaborate and hazardous isotopes, rendering the underlying technique not so eco-friendly. In the present- and next-generation massive application of silicon solar cells (both in consumer applications as well as in space/military situations), a preemptive testing can facilitate mitigating the factors that could cause device failures due to IoR exposures. Further, such tests could accommodate accelerated testing/aging methods, so as to duplicate/emulate the effects of low-level IoR dosages over an extended period of exposures (as in space-missions) [7].

To ascertain the effects on solar-cells vis-à-vis ionizing radiation indicated here is a novel method that involves:

  1. Experimental techniques sans isotopes via simulating ionizing radiation fluence via electrical overstressing (EOS).
  2. A method compatible for preemptive and quick evaluations in situ of the devices-under-test (DUTs). The underlying test method follows EOS applied to DUTs (solar-cells) and correlating the EOS level to ionizing radiation fluence. The electrically over-stressed devices can be subjected to both physical and/or electrical evaluations in order to ascertain the extent of damage occurred.
  3. The test method proposed can be adopted for accelerated test/aging procedures.

Inasmuch as high-energy particle sources/isotopes are avoided, this is totally an eco-friendly approach.

Description of the Method

Shown in Fig. 1 is the experimental set-up. The DUT is zapped with a sequence of several electrostatic impulses from an appropriate instrument. (The DUT is forward- or reverse-biased as necessary). The zap level (voltage) and the number of zaps (impulses) applied can be correlated to equivalent ionizing radiation fluence as indicated by one of the authors elsewhere [8] and as illustrated in Fig. 2.

Under pre- and post-zap conditions, an ensemble set of typical (and commercially available) Si pn-junction solar cells were subjected to:

  • Evaluations of forward and reverse current-voltage (V-I) characteristics
  • Measurement of ac impedance characteristics

Results obtained thereof indicate that the forward characteristics are hardly affected but, the reverse V-I characteristics as well as ac impedance values (across a frequency range) show significant alteration after the DUTs were zapped. Sample results on the coefficients of observed variations are presented in Fig. 3 and Fig. 4 shows normalized diode impedance versus frequency. It is surmised in this study that such observed changes stem from the EOS (that denotes equitably the ionizing radiation fluence). The basic aspects of equating EOS versus IoR levels are comprehensively discussed in [8-12] with reference to MOS devices. The relevant concept is extended in this study.

Accelerated Testing/Aging Model

Cumulative build-up of degradation with the recurrence of zaps amounts to a dormant stage of failure during which the device may exhibit degraded performance with out-of-specs condition. Such device aging can be done via accelerated testing [8- 10].

Fig. 5 illustrates qualitatively the so-called equivalent aging principle of accelerated testing of the DUTs. Suppose DG is some measurable degradation level of the DUT versus the extent of degradation inducing mechanism (such as ionizing radiation). Further, suppose the DUT is tested under two stress level S1 and S2 with S1 > S2. (Relevant to the present study, S1 and S2 correspond to a higher and a lower temperature respectively).

Now, given a curve (a) obtained with low-stress level (S2), corresponding curve (b) depicts the result with S1 > S2. Normally the functional forms of (DG) versus dosage (ds) remain identical in shape regardless of S1 and S2 (similitude principle). In Fig. 5, d1 and d2 are known as equivalent dosages of the similitude model. And, corresponding equivalent aging coefficient η can be defined as [12-15]: .

η = [ln(d2/d1)]/ln[(S1/S2)]

Thus, by equivalent aging principle evaluating the degradation at a (low-dosage and high-stress) level will lead to evaluating the degradation at a (high-dosage and low-stress) level. In the current study, the stress S1 and S2 adopted correspond to higher (93°C) and lower temperature (21°C) testing of the DUTs, which have shown distinct results on degradation.

Essentially, the observed degradations in the post-zap devices are attributed to marked elevation in surface carrier levels and formation of traps (and/or discontinuities) in the semiconductor bulk region [16, 17]. Variation in the surface condition due to IoR/EOS manifest as changes in the surface resistance, significantly affecting the reverse V-I characteristics. The bulk effects induced mostly influence the mobility degradation manifesting as capacitive effects implicitly affecting the ac impedance assessed.


References

  1. A.H. Johnston, “Radiation damage of electronic and optoelectronic devices in space,” 4th International Workshop on Radiation Effects on Semiconductor Devices for Space Application, (Tsukuba, Japan, October 11-13, 2000).
  2. N. Wyrsch, D. Domine, F. Freitas, L. Feitknecht, J. Ballif, G. Poe, K. Bates and K. Reed, “Ultra-light amorphous silicon cell for space applications,” 4th World Conference and Exhibition on Photovoltaic Solar Energy Conversion, (Waikoloa, Hawaii, May 2006).
  3. T.V. Torchynska and G. Polupan, “High efficiency solar cell for space applications,” [Online]. Available: http://redalyc.uaemex.mx/pdf/942/94217305.pdf (Accessed on: Oct 14, 2010).
  4. T.V. Torchynska and G.P. Polupan, “III-V material solar cells for space application,” Semiconductor Physics, Quantum Electronics & Optoelectronics, Vol. 5(1), 2002, 63-70.
  5. A.F. Meftah, N. Sengouga and A.M. Meftah, “Prediction for the performance degradation of GaAs solar cells by electron irradiation,” [Online]. Available: http://www.cder.dz/ download/Art11-4_12.pdf (Accessed on: Oct 14, 2010).
  6. R.D. Schrimpf, “Radiation effects on embedded systems,” Springer Verlag, The Netherlands: 2007, 11-29.
  7. J.F. Salzman, “Preemptive testing can mitigate cosmic radiation effects,” Power Electronics Technology, Vol. 36(4), April 2010, 36-38.
  8. S.O. Agbo, P.S. Neelakanta and L.M. Lay, “Reliability assessment of CCDs operating under ionizing radiation ambients: Failure-simulation studies via electrical overstressing,” Microelectronics Reliability, Vol. 32(7), 1992, 1029-1042.
  9. P.S. Neelakanta and R.I. Turkman, “Noise characteristics of ionizing-radiation-stressed MOSFET devices,” Solid State Electronics, Vol. 30(6), 1986, 673-674.
  10. P.S. Neelakanta, R.I. Turkman and T.K. Sarkar, “Susceptibility of on-chip protection circuits to latent failures caused by electrostatic discharges,” Solid State Electronics, Vol.29(6), 1986, 677-679.
  11. P.S. Neelakanta and R.I. Turkman, “Analogous influence of ionizing radiation and electrical overstressing: Damage characterization via noise parameters,” Natural Space Radiation and VLSI Technology Conf. (Houston, TX, January 20-21, 1987).
  12. P.S. Neelakanta and R.I. Turkman, “Noise performance studies to assess MOS-device degradation due to impulsive overstresses,” Conf. Record: 1986 IEEE Intl. Symp. on Electrical Insulation (Washington D.C ,1986), 327-330.
  13. L. Simoni and G. Pattini, “A new research into the voltage endurance of solid dielectronic,” IEEE Trans. Elec. Insulation, Vol. 28, 1975, 17-27.
  14. C.C. Yu, “Degradation model for device reliability,” Proc. Reliability Phys. Symposium (1980), 52-54.
  15. E.B.W. Lo, R. Phelps and S. Michael, “Evaluation and testing of the solar cell measurement system onboard the naval postgraduate school satellite NPSAT1,” 22nd AIAA International communications satellite systems conference & exhibit, (Monterey, CA, 9-12 May, 2004).
  16. M. Yamaguchi, “Radiation-resistant solar cells for space use,” Solar Energy Materials & Solar Cells, Vol. 68(1), 2001, 31-53.
  17. A.R. Jha, “Solar cell technology and applications,” Auerbach publications, Boca Raton, FL: 2010.
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