Large steel buildings, automobiles, mountains, even people survive real atmospheric lightning. Humans can also create their own miniature lightning bolts (sparks) and survive. When those sparks reach an IC, however, major trouble results. Nanometer-tall transistors need protection to survive even human sparks. We will discuss ways to protect printed circuit boards (PCBs) against ESD destruction. We will show that analog parts with bigger geometries are the best to use to protect a field-programmable gate array (FPGA) with its small geometry. By taking these measures, the ICs in an FPGA remain more reliable and deliver consistent quality performance.
Where do human-generated sparks come from? They are caused by a triboelectric charge. This happens when two materials come into contact (rubbing helps) and are then separated. Some electrons will transfer to one of the items. How many electrons move and to which surface depends on the material’s composition. This is a common phenomenon because almost all materials, insulators, and conductors exhibit triboelectric properties. For example, rubbing a balloon on one’s hair, and walking across a rug can all exhibit the triboelectric effect.
A tutorial on the fundamentals of electrostatic discharge1 illustrates the voltages that humans produce during various activities. Table 1 lists those voltages versus relative humidity (RH).
No wonder it hurts when we walk across a rug and touch a doorknob! A general rule is that 5,000V can jump about one centimeter (0.4 inches) in 50% RH air. For someone five or six feet tall this is a spark; it is painful, but we survive. Now change your perspective. What havoc would that spark cause to something a few micro-inches tall, like a transistor in an integrated circuit (IC)? In this situation, a centimeter spark is a massive, frightening, lightning display.
Now, we can turn to ICs. Microprocessors have long led the density improvements of digital semiconductors. Fabrication technology has resulted in smaller and smaller transistors. In 1971 the Intel® 4004 computer processing unit (CPU) was introduced in a 10μm geometry. In the 1980s and 1990s the process made parts smaller than a bacterium. In 2012 ICs are approaching densities 1,000 times smaller than the 1971 technology and the features on the chip are smaller than virus. In 2012, one can buy field-programmable arrays (FPGAs) with 28nm features and 6.8 billion transistors in one package, and the future promises to double that density in the next few years. The small transistors are closely packed together and need to operate on low voltages (typically 1V and below) to control the heat generated.
To put 28nm in perspective, note the zeros: it is 28 billionths of a meter (0.000000028). Let the distance between San Francisco and New York City represent one meter (about 4000 kilometers or 2500 miles). Now 28nm (one part in 36 million) is 0.11 meters or 4.4 inches. How big must a lightning bolt be to damage such small geometry devices and how does one protect such necessary and useful FPGAs?
The easy answer is to use the very I/O interface devices that bridge the digital and analog worlds. Analog mixed-signal ICs are made in comparatively large geometries (10 to 100 times larger than digital) and with higher voltage (typically 20V to 80V and higher), which make them more robust than the tiny digital transistors. Though today’s analog mixed-signal devices are generally tolerant of ESD, they do benefit from discrete ESD devices.3
Semiconductor manufacturers take electrical overstress (EOS) and electrostatic discharge (ESD) very seriously. First, for the obvious reason, that EOS and ESD can destroy parts during fabrication, package assembly, and test. But more importantly, these negative forces directly impact the quality and lifetime of the circuit in the customer’s hands.
At first a part that is electrically overstressed may appear to function properly. It might even function in a slightly degraded manner but still pass the automatic test equipment’s (ATE) examination, only to fail later in the field. EOS and ESD failures are preventable and are, without doubt, critical quality control issues.
Building an IC in manufacturing is the first place where EOS and ESD damage can occur. (Fig. 1(a)) shows a schematic diagram of the PC board (PCB). We might think that the IC is protected by the series capacitor. This is not the case. The second opportunity for damage is when the customer mounts the IC on a PCB to build a product. Looking closer at Fig. 1(b) we see that the capacitor has a 50V working voltage, but the distance between the two metallic end connections is only 0.28 inches (7mm). Since the spark just jumped 0.4 inches (1cm), the small gap around the capacitor is easily compromised. The result may be that the IC pays with its life (Fig. 1(c)). Finally, the EOS or ESD damage can occur when the customer operates the product in their environment.
There certainly are many opportunities for considerable damage. We can actually see the result of EOS and ESD destruction inside an IC. To do this, the package epoxy material must be removed. This is usually done with hot acids in a double-glove isolation box. This process is incredibly dangerous. The fumes are deadly. One breath will cause a painful death; one drop of acid on human skin would result in, at best, the amputation of a hand or arm, or at worst death.
Microphotograph (Fig. 2(a)) shows no apparent damage. The bond wire and pad labeled REF is provided so we can orient ourselves and compare photos. The liquid crystal material is painted on the die (pink color) and is similar to the liquid crystal used in mood rings and children’s forehead thermometers. It changes color with small changes in temperature. When power is applied to the IC, the area drawing excess current, marked here with a yellow box, heats and changes color. It is a hot spot. This is interesting, but what caused the problem?
The REF bond wire (Fig. 2(b)) indicates that this image is rotated 45 degrees. As we progressively zoom in, we see electro migration. The EOS has caused a short circuit as the damage grew under the influence of the electrical stress. This process can happen over time and progress during many short stresses until, suddenly, the part fails.
For comparison, now we examine another IC where a lightning bolt caused quick destruction (Fig. 3).
Again the “7” in the upper left corner of each image in Fig. 3 is for orientation. There is not much to see under visible light, but under magnification the liquid crystal shows the temperature rise and resulting EOS.
Fig. 4 plots the data from the circuit in Fig. 3 and we see that the known good part exhibits a clean, repeatable plot. The current increases in the vertical axis with 4.5V applied. When the current approaches 250µA, a knee is formed; as the voltage increases, the current stays at 250µA. Fig. 4 also shows that the defective part continues to draw more current above the knee.
Under closer scrutiny, part serial number 1 (SN1) shows a hole in the gate oxide (Fig. 5). The lightning bolt shorted the gate to the substrate causing excess current to flow. Of course, the transistor paid with its life. Typical gate oxide is 5nm to 15nm in thickness, depending on the fabrication process. In dense digital microprocessor parts, the oxide may be 1.2nm to 3nm thick. To illustrate how thin that is, in silicon 1.2nm is ~5 or 6 atoms thick. Thus, to a gate that is a few nanometers tall, almost any spark is a giant lightning bolt.
Protect the Circuit
The rise time of a spark is very fast, so any way that we can slow it down will reduce the peak voltage. ESD structures (Fig. 6 and Fig. 7) are typically used in two places in a system: at the board level inputs and outputs with series resistors; and inductors along with capacitors to ground that can act as a lowpass filter. PCBs are thus protected from EOS/ESD by a combination of discrete silicon (small signal or reference) Schottky diodes, avalanche (Zener) diodes, transient voltage suppression (TVS) diodes, gas-tube discharge devices, resistors, inductors, and metal oxide varistors (MOVs).
The ESD structures of Fig. 7(a) through (c) are internal to the ICs. External discrete components used for EOS/ESD protection tend to be physically larger and carry larger currents. In addition to the ESD protection build into many products, specialized ESD protection devices like the MAX14541 and MAX3203 are available to designers.
It is important to note that many circuits have built-in EOS/ESD protection, even though that is not their primary function. Consider for a moment the MAX5481 family of 10-bit nonvolatile (NV) potentiometers, the MAX5134 quad 16-bit DAC, and the MAX6001 family of low-power, low-cost voltage references. A close look at the data sheets shows that ESD is not mentioned. But the ESD specification depends on the IC fabrication process and is stated on the reliability reports for each part. You can find the ESD information by starting at the QuickView page for each part on the Maxim Integrated Products website. Near the bottom of the page is the technical documents area and the reliability report.4 A click here brings up the reliability report page. If the reliability report is not online, it can be requested.
- ESD Association, ESD Fundamentals, An Introduction to ESD Part 1, © 2001, Rome, NY at www.esda.org/esd_fundamentals.html.
- Xilinx, Device Reliability Report,” Table 1-7: Wafer Process Technology Family,” Fourth Quarter 2011, Page 15, http://www.xilinx.com/support/documentation/user_guides/ug116.pdf.
- Maxim Integrated Products tutorial 4991, “Oops...Practical ESD Protection vs. Foolhardy Placebos,”and tutorial 1167, “Practical Aspects of EMI Protection.”
- Some example excerpts of EOS/ESD protection from those reliability reports:
Reliability Report for MAX5482EUD+2 (MAX5481, MAX5483, MAX5484). “Item C.) E.S.D. and LatchUp Testing; The DP22-1 die type has been found to have all pins able to withstand a HBM (human Body Model) transient pulse of 2500 V per JEDEC JESD22-A114-D.” For the complete report, go to http://www.maxim-ic.com/reliability/product/MAX5482.pdf .
4AGTG+3, “Item C.) E.S.D. and LatchUp Testing; The DB34 die type has been found to have all pins able to withstand a HBM transient pulse of +/-1500 V per JEDEC JESD22-A114-D.” For the complete report, go to http://www.maxim-ic.com/reliability/product/MAX5134A.pdf.
Reliability Report for MAX6001EUR+4 (MAX6002, MAX6003, MAX6004). “Item C.) E.S.D. and LatchUp Testing; The RF23-6 die type has been found to have all pins able to withstand a HBM transient pulse of 2500 V.” For the complete report, go to http://www.maxim-ic.com/reliability/product/MAX6001.pdf.