EET
Circuit topology boosts power density in power conversion platforms

Circuit topology boosts power density in power conversion platforms

A new circuit topology from CUI Inc. helps engineers get in synch with the four major trends in power conversion devices: higher power densities, more efficiency for “green” applications, faster transient responses, and lower EMI. The topology, dubbed Solus, is currently used in CUI's quarter-brick bus converter with 720 W of output power.

Solus topology combines a single-ended primary-inductor converter (Sepic) with conventional buck topology to form a Sepic-fed buck converter. Lower voltage and current stresses in the topology, coupled with an inherent GCE (gate charge extraction) process, lets Solus reduce switching turn-on losses by 75% and switching turn-off losses by 99% on its control FET, when compared with conventional buck converters. Distributing the energy delivery among multiple paths reduces circuit conduction losses by nearly 50% and further improves efficiency. This lets the topology provide 40% more output current without taking up more space.

Portioning out operating currents into several paths also cuts reduction losses. And the multi-current paths reduce voltage stress on components by almost 50%, possibly enabling the use of lower-voltage MOSFETS and capacitors, compared with standard buck converters. And because input current is almost straight dc with only slight ripple, input capacitors can be about 95% smaller than those of conventional converters. This same feature reduces EMI due to input current ripple.

Resources

CUI Inc., Tualatin, Ore. www.cui.com

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish