Known-good-die (KGD) sort is a commonly used technique in semiconductor processing that allows IC device engineers to bypass the packaging of defective semiconductor devices, saving time and money. Due to inadequate probes and probe stations, power-device engineers have not been able to take advantage of this technique for the parameter of RDS ON in power MOSFETs, and have had to resort to a lengthy and costly packaging process prior to characterization.
However, using a recently developed probe technology featured in the Tesla power-device-characterization system, the capability now exists to perform these RDS ON measurements directly on the wafer over a broad temperature range. This provides power-device designers with the capability to obtain a wafer map of device RDS ON values for each die on the wafer. This means designers can determine KGD much earlier in the manufacturing process, reducing both development times and manufacturing costs for the device.
As a general rule of thumb, every manufacturing step in the design and development process increases total project cost by a factor of 10. Therefore, the elimination of unnecessary packaging enabled by on-wafer RDS ON measurements can substantially reduce design-cycle times and development costs for power devices. Furthermore, this on-wafer test capability can be used to screen power devices for lowest on-resistance to achieve superior performance in the application.
Key Power Measurements
In the engineering design and development process, it is vital to verify as many parameters of a manufactured device as possible, and to do so as early as possible in the manufacturing process. The worst thing that can happen is to get to the end of the process and discover that a package failure may have rendered a device untestable. Without KGD data, the cause of a failure cannot be known.
By testing on-wafer, the painful process of finding the root cause of failure in a packaged device is precluded. If a device fails the wafer testing, it will not be packaged. Conversely, if a packaged device fails, either the packaging design or the packaging process is the most likely cause, because the device would have tested good prior to being packaged.
Power MOSFET engineers are confronted with the conflicting demands of providing ever-increasing efficiency and power ratings, while using ever-shrinking process geometries. Traditionally, the solution has been to drive device RDS ON values to lower and lower levels. In general, lowering the on-state resistances of power devices improves their performance. Therefore, RDS ON is a key parameter for power-device manufacturers and can be used as a basis for KGD sorting.
The capability to sort devices based on drain-source resistance, or even the capability to measure the through resistance of the device early in the manufacturing process, is important. Such capabilities can enable power-device engineers using leading-edge process technology to design better, more stable fabrication processes for their devices. Processes with these capabilities also can be controlled, modeled, characterized and optimized more effectively by fabrication-process development engineers, dramatically improving process yield.
The basic steps for performing and verifying the key power measurements of a field-effect power semiconductor device are essentially the same for both on-wafer testing and in-package testing. RDSON of the device is derived by dividing the drain-source voltage by the drain-source current. The maximum current rating of the device for a given power rating that might be assigned for a given package type can then be determined by sorting based on the key parameter of RDS ON.
Both voltage and current usually can be measured directly and accurately from the parameter analyzer's source-monitoring units (SMUs) for low-power on-wafer testing. This is accomplished by using the proper Kelvin connections (Fig. 1). However, in the case of high drain-source currents in a power MOSFET, the resistance of the device under test (DUT) may be much lower than the resistance of the SMU test leads, causing significant voltage drops that easily distort the voltage measurements.
To avoid test-lead voltage-drop errors for large currents, all parameter-analyzer SMUs offer “force-and-sense” connections, enabling true Kelvin test conditions. As the drain-source current increases, it causes a proportionally higher voltage drop, or force, in the test leads. The “sense” connection measures the voltage drop, which is then supplied to the SMU for calculating the actual drain-source voltage.
Most engineers try to make the key RDS ON measurement directly from a parametric analyzer's Kelvin-connected SMUs. However, even when the parameter-analyzer SMUs are connected in a true Kelvin measurement, significant errors in the derived value for RDS ON have been observed. These errors are mostly due to the voltage accuracy or resolution of the SMU itself.
The RDS ON values derived in Fig. 2 use the voltage read from the current-source SMU, yielding 40 mΩ. Fig. 3 shows the same device with a voltage-monitoring unit (VMU) added to accurately measure the source voltage used in the RDS ON calculation, yielding 12 mΩ. If very-high-power devices are to be fully characterized directly from the parametric analyzer, it requires that a VMU be applied to the source probe (or, in some cases, both the source and drain probes) in order to get accurate measurements at high currents.
In the packaging process, the die is bonded to the package; therefore, there is no significant resistance between the package and the die. Measuring RDS ON in a packaged device is beneficial because it accurately simulates the behavior of the die in the situation in which it will be used. The drawback is the time and cost required to package the die.
Wafer-level measurements are convenient and provide a time and cost savings that are invaluable to process-development engineers. The ideal scenario is to marry the accuracy of in-package measurements with the time and cost savings of on-wafer testing.
Until recently, the primary roadblock to performing wafer-level measurements was at the wafer-to-chuck interface. The electrical resistance between the chuck and the backside of the wafer was significant. Consequently, when engineers tried to sort die by the value of the RDS ON measurement, the outcome was actually the sum of the RDS ON of the device plus the resistance of the chuck-to-wafer interface, degrading the measurement and skewing results. With such poor measurements, it is not possible to accurately characterize the die.
A methodology and tools are needed to test the wafer under the exact conditions it will encounter once packaged. As with all measurements, the goal is to make the measuring tool's effect on the measured parameter negligible. Therefore, the test tools should be transparent to the DUT. For the ideal solution to the problem of measuring power devices on the wafer, this kind of transparency can be achieved by minimizing the resistance between the chuck and the backside of the wafer.
Until recently, there were no wafer-chuck technologies that allowed an on-wafer RDSON measurement to correlate wafer-level measurements with in-package measurements. However, Cascade Microtech's VacuChannel technology addresses the on-wafer RDS ON measurement challenge, providing a unique chuck that distributes the vacuum more evenly to the wafer than standard holes or ring technologies.
The evenly distributed vacuum, coupled with a highly polished gold-top surface, ensures 10 to 100 times lower contact resistances between the wafer and chuck than what is offered by standard chuck technologies. The VacuChannel technology is available in the Tesla on-wafer power-device-characterization system, which performs measurements over temperature at currents up to 60 A and voltages up to 3000 V.
In addition to providing low contact resistance, VacuChannel technology offers superior handling of thin wafers. The advanced microchannels will hold down wafers as thin as 80 m. Previously, thermal warping, or “potato chipping,” of the wafer compounded the problems of wafer-level probing for power devices. This occurs because the thickness of power-device wafers are typically reduced for improved die performance, reducing their lateral thermal conductivity. VacuChannel technology significantly reduces the thermal resistance of the contact between the backside of the wafer and chuck, providing superior hold-down capability of the power-device wafer.
Using this technology, a true parametric measurement of a particular die for multiple gate-source voltages can be performed at the wafer level (Fig. 4). This figure contains data for three different metals used for the top-surface contact of the chuck. The critical RDS ON measurement can be made for each device much earlier in the engineering-development manufacturing process. This eliminates the need to dice, package, test and then finally sort faulty power devices that might have passed conventional low-power functional testing.
With effective wafer-level testing, all of these steps can be eliminated. For example, referring to the wafer map in Fig. 5, 109 devices were tested in less than 15 minutes using the wafer-testing methodology, as opposed to the conventional multistep process previously described.
To replicate the results obtained from wafer-level RDSON, power-device engineers would need to use the following procedure: First, perform a voltage test; second, verify each good die with repeated testing; third, sort out the good die from the bad die; fourth, mark the location of each good die on a wafer map; fifth, cut the wafer into individual die; sixth, pluck and package each good die; and seventh, individually measure RDS ON for each packaged device.
Clearly, this conventional process is prone to error. It also takes at least three to four hours of processing, whereas the on-wafer method takes only 15 minutes. Furthermore, when testing system-on-chip (SoC) devices — as opposed to the discrete devices that have been the focus of this discussion — the potential savings from using full on-wafer testing are even greater.
Wafer-level testing also has tremendous advantages for intelligent power modules (IPMs). Without wafer-level testing, the final yield of a module is potentially reduced, starting with the yield of a single die, and decreasing for each additional semiconductor device in the module. Moreover, perfectly good devices are wasted when co-packaged with faulty devices within the same module. The best solution for this problem is the use of a prepackaging test methodology, such as that enabled by wafer-level testing.
Testing Over Temperature
Another important SoC testing capability for power devices is to test the device over a broad temperature range. For example, when designing a power supply, it may be necessary to guarantee operation in both the heat of remote deserts and the cold of Earth's orbit. Therefore, thermal characterization in conjunction with full functional testing of the SoC is critical.
This means that each SoC device on a wafer requires full functional testing and characterization for all possible system voltages and all logical input combinations. These tests must be conducted over the operating and storage-temperature ranges for KGD sorting. This level of testing is especially important for military and aerospace applications.
With the dramatic improvement in the heatsinking properties of the VacuChannel chuck technology, testing on-wafer over a wide temperature range is possible. Thermal conditions once restricted to the testing of packaged devices can now be created for the testing of wafer-level devices.
On average, the thermal resistance of a normal chuck is 1°C/W, and a typical wafer chuck can exhibit a 50°C temperature rise. This has effectively prevented on-wafer thermal testing. Specifically, thermal runaway can render electrical measurements useless and can even cause electrical shorts in the measurement path.
VacuChannel technology provides a heatsinking capability that is an order of magnitude greater than that of conventional wafer chucks, enabling full temperature range measurements from -55°C to 200°C. During testing, it was found the temperature rise on any DUT using the technology was less than 0.1°C/W, reaching 75 W/cm2 and even 100 W/cm2 on power-dissipating devices. During these tests, the small temperature increases in the DUT allowed testing across a broad temperature range. This is in contrast with a standard thermal chuck, which could not restrict the temperature and frequently caused thermal runaway in the DUT.