Power Electronics
Ultralow Jitter OTN Clock Translator in the Smallest Footprint

Ultralow Jitter OTN Clock Translator in the Smallest Footprint

Microsemi Corporation announced its new ZL30169 high performance Optical Transport Network (OTN) clock translator fully compliant with the ITU-T G.8251 standard that ensures interoperability and satisfactory network performance. The ultrasmall, three-input, three-output any-rate-to-any-port clock translator for OTN provides output clocks with industry-leading jitter performance of 250fs RMS, ideal for 100G coherent optical networks.

According to market research firm Infonetics, 100Gb/s is the next speed of choice in 2015 to 2030 with greater than $10 billion in revenue expected by 2018, mostly from service providers. In CY13, the number of 100G ports shipped quintupled to 70,000. The new 100G coherent technology enables transport of 100G data rate across long distances, up to 2500km.

The ZL30169 integrates a digital phase locked loop (DPLL), analog PLL (APLL) and EEPROM into an ultrasmall 5x5mm 32-pin QFN package. The APLL generates the ultralow jitter output clocks programmable to any frequency from 1Hz to 1035MHz, the first device of its kind offering such a wide range. With programmable loop bandwidth from 14Hz to 500Hz, the DPLL accepts any input frequency from 1kHz to 1250MHz and provides hitless reference switching, holdover and jitter filtering. The EEPROM provides automatic self-configuration of the device at start-up. The ZL30169 has the critical features such as dynamic rate conversion for forward error correction used in OTN transport and switching applications. The ZL30169 meets all the jitter and wander requirements that are specified in the ITU-T G.8251 Recommendation to ensure satisfactory network performance.

The ZL30169 also offers Numerically Controlled Oscillator (NCO) mode in which output frequencies can be controlled with very high resolution (better than 0.01ppb) by system software. This capability provides a cost-effective solution for customers designing their own Mapper with FPGAs to replace large, expensive, fixed-frequency voltage-controlled oscillators (VCXOs).

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