Power Electronics
Receiver Reduces EMI and Power Consumption

Receiver Reduces EMI and Power Consumption

The SN65LVDS822 is an advanced FlatLink™ LVDS receiver designed on a modern CMOS process. It has several unique features, including three selectable CMOS output slew rates, CMOS output voltage support of 1.8 V to 3.3 V, a pinout swap option, integrated differential termination (configurable), an automatic low-power mode, and deserialization modes of 4:27 and 2:27. It is compatible with TI FlatLink™ transmitters such as the SN75LVDS83B, SN65LVDS93A, and standard industry LVDS transmitters that comply with TIA/EIA-644-A.

The SN65LVDS822 implements five low-voltage differential signal (LVDS) line receivers: 4 data lanes and 1 clock lane. The clock is internally multiplied by 7 or 14 (depending on pin MODE14), and used for sampling LVDS data. The device operates in either 4-lane 7x mode, or 2-lane 14x mode. Each input lane contains a shift register that converts serial data to parallel. 27 total bits per clock period are deserialized and presented on the CMOS output bus, along with a clock that uses either rising- or falling-edge alignment.

A clock frequency range of 4 MHz to 54 MHz is supported in the standard 7x mode, which is to be used with LVDS data rates of 28 Mbps to 378 Mbps. The 14x mode supports 4 MHz to 27 MHz, for LVDS data rates of56 Mbps to 378 Mbps. The LVDS clock frequency always matches the CMOS output clock frequency. DC common mode voltage is monitored on clock line for normal operation. The device is designed to support resolutions as low as 1/16th VGA (160x120), and as high as 1024x600, with 60 frames per second and 24-bit color.

TAGS: Products
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.