Power Electronics

Controller IC Employs Real-Time Adaptive Loop Compensation, PMBus

Controller IC combines power management and mixed-signal functions that implement adaptive control of closed loop compensation. This SoC consists of a DSP and RISC processor, RAM and non-volatile memory, power conversion blocks, SMBus serial interface, ADC and DAC, and timing sources.

 

Saying that Powervation’s PV3012 is a dual phase digital synchronous buck controller for point-of-load (POL) applications doesn’t adequately describe the IC. Even adding that the IC is PMBus™ compliant still doesn’t fully describe the PV3012.

In fact, the PV3012 is all of the above, plus real-time adaptive loop compensation technology called Auto-Control®. This patented digital control loop technology optimizes the trade-off between dynamic performance and system stability on a cycle-by-cycle basis without requiring any noise injection or other drawbacks of part-time measurement techniques. This is a key advantage for designs that drive imprecise or variable loads, and compensates for power supply component parameter drift that occurs over temperature and time. This approach also relieves power supply designers of the burden of compensation, plant characterization, and reduces total design iterations. Furthermore, Auto-Control readily enables efficiency maximization mode changes such as phase add/drop and light-load modes. Auto Control also improves transient response as illustrated in Fig. 1 that shows supply output with and without Auto Control.

PV3012’s proprietary Auto-Control technology brings true adaptive control into the DC/DC power conversion domain. The technology:

  • Simplifies designs used in uncontrolled products by second party users (e.g., modular power converters)
  • Allows a broad range of end configurations
  • Lowers solution and design-phase costs by reducing the amount of design margin required to design for unknowns
  • Improves the reliability of the product and reduced time and cost related to field failures and troubleshooting
  • Reduces the time required to develop and test the power supply
  • Develops power supply solution blocks that are simpler to replicate for your future design projects

 

The PV3012 includes a lean Digital Signal Processor (DSP) and a Reduced Instruction Set Computing (RISC) Processor, with a precision data acquisition system. The dual-core architecture produces a voltage regulator for applications that demand flexibility of potential loads or use loads that may change over the lifetime of the power supply, The IC uses a discrete-time adaptive control algorithm updated in real-time, on a switching cycle-by-cycle basis, running on the DSP core to implement closed loop compensation, eliminating external compensation components or the need to manually retune the compensation, should the characteristics of the load change (load capacitance, inductances, etc.). The DSP core is optimized for high performance with low power consumption, as the optimization of the adaptive algorithm is independent of general housekeeping, fault management and configuration tasks.

Anti-Fused NVM

The PV3012’s digital power management system utilizes RAM and non-volatile memory (NVM) to perform their tasks, and to provide designer flexibility. Both the program code and PMBus parameters are stored in NVM. When powered on, the contents of the NVM are loaded to the RAM for fast access to the processing unit. The NVM serves as a long-term storage of vital code that determines functionality of the power supply; therefore it is crucial that this memory be reliable.

The IC uses anti-fused based NVM to ensure maximum fidelity of the data stored, over elevated temperatures and time. The NVM provides memory for custom configuration of the product, storage for pre-loaded configuration tables, and storage for firmware code. While this NVM is one-time programmable, the SoC provides enough onboard NVM for multiple writes to memory, such as adjusting values in configuration tables. Programming of anti-fused based NVM causes a permanent structural change, does not suffer from charge leakage (as found in some memory technologies), and is not reversible with voltage or temperature. This memory does not suffer from acceleration mechanisms related to high temperature stress (HTS), so anti-fused based NVM provides a reliability advantage for designs that operate in elevated temperature environments and for designs that need to guarantee data retention for long periods of time. This NVM is specified from -40°C to 125°C junction temperature with a 20-year data retention rating

ADC

A low-latency, precision 11-bit ADC samples and quantizes voltages, currents, and temperatures. The results are passed to the DSP, which solves the resulting matrix and adjusts the digital pulse-width modulator (DPWM) output on a cycle-by-cycle basis. The DPWM provides duty cycle resolution of at least 15 Bits, effectively eliminating limit-cycling and quantization noise. ADC results are also passed to the power management processor, which in turn provides the values through the PMBus communication interface for system telemetry (remote measurement and reporting) of current, voltage, and temperature information. To maximize system performance and reliability, the IC provides temperature correction/compensation of several parameters.

This PMBus compliant controller uses full differential measurements and the ADC to provide precision system telemetry. To enhance system performance and reliability, the PV3012 delivers advanced digitally mapped temperature compensation of key parameters, enabling current measurement precision of 3% over the full load range.

Gate Driver

Fig. 2 shows a typical application of the PV3012 with external gate drivers that accept PWM inputs and drive synchronous multiphase MOSFET outputs. This power supply can consist of a single-phase, or two-phases interleaved (dual-phase mode), with a single PV3012. For systems that require additional phases, the PV3012 supports parallel scaling of multiple controllers. This support includes: communication over the Digital Stress Share (DSS) line, phase add/drop, phase current sharing, synchronization line (SYNC), and system good line (SYSG).

The DSS is a proprietary single-wire digital communication bus for the interconnection of multiple paralleled digital control ICs. It is a combination of a master/slave current sharing architecture with a quasi-democratic average current determination. The master/slave architecture ensures tight line and load regulation, whereas the average current reference for each phase is a result of the current reading from each phase (democratic). This active phase current balance provides asymmetric current sharing to help eliminate “hot spots” and the devices participating in DSS gain knowledge of the highest and lowest stressed device and adjust control to match the average system stress. DSS improves efficiency, simplifies thermal management, improves reliability, and provides a higher level of redundancy.

The PV3012 interfaces to industry-standard MOSFET drivers through PWM1 and PWM2 signals, as well as multi-purpose driver-mode outputs DMD1 and DMD2 (Fig. 2). When selecting a MOSFET driver, ensure that the input level thresholds (high, low, and tri-state band) of its PWM and Enable (if present) are compatible with the 3.3 V drive levels supported by the PV3012. Most popular MOSFET drivers fulfill this criterion. Fig. 3 shows the details of PWM and DMD signals for phase 1 (PWM1 and DMD1). Phase 2 signals PV3012 V1.0 (PWM2, DMD2) are the equivalent signals for phase 2 in a dual phase application.

The PV3012 supports two basic MOSFET driver types:

  • Active High Tri-state PWM input
  • PWM input with Enable input
Table 1 PV3012 Protection Features
Protection and Fault Detection Programmable Thresholds Programmable Response Time Non-Latching with Auto Restart Temperature Compensated
Output OVP Yes   Yes  
OCP Yes Yes Yes Yes
SCP Yes   Yes  
LOS Yes Yes Yes  
Input ULVO & OVLO Yes   Yes  
OTP(Internal, On-Chip Sense) Yes Yes Yes  
UTP(Internal, On-Chip Sense) Yes      
OTP(External Sense) Yes   Yes  
UTP(External Sense) Yes      

 

The PV3012’s DPWM must control each power switch in the power stage independently. Each output phase employs two power switches: the high-side (control) switch, and the low-side (sync) switch. During operation of the sync-buck converter, either one power MOSFET is on, or both power MOSFETs are off, at a given time. Whenever power conversion is disabled (due to a fault condition, or power conversion disabled through CTRL pin or PMBus command), both switches will be held off.

This controller may be used in single or dual phase mode. In the dual phase mode, phases may be added or removed as the load varies, so that efficiency is maximized over the load range. Also, the output of each phase is interleaved, which doubles the effective output switching frequency. With DSS and PLL synchronization, multiple PV3012 devices may be used in parallel to increase the number of phases supporting the application’s load. Auto-Control, adapts on a cycle-by-cycle basis and provides active loop compensation to stabilize the control loop as phases are added and removed. PV3012 delivers voltage precision of ±0.5% over line, load, and the full -40°C to 125°C junction temperature range. The converter’s output can be configured from 0.6 V to 5.5 V using PMBus™ commands or with an external resistor to access standard and DOSA set-point tables. As shown in Fig. 2, the PV3012 has two supply pins. VDD33A is the supply pin for the analog circuitry, whereas the VDD33D is the supply pin for the digital circuitry. Both pins require a typical voltage of 3.3 V, and it is recommended to use a 0.1 μF, X7R decoupling capacitor at each pin.

 

 

 

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish