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For decades, 50 V was the maximum voltage rating available for solid SMD tantalum capacitors. With today's requirements for power distribution in the range of 28 V and upward, especially in the avionics, military, and space industries, higher-voltage SMD tantalums are needed for reliable operation in demanding applications.
The stress on the Ta2O5 tantalum dielectric material of a SMD solid tantalum capacitor is due to a combination of available current, voltage, and temperature. Solid tantalum reliability models such as MIL-HDBK-217 show us that reducing any one of these three stresses yields improvements in the reliability levels required by today's demanding industrial, military, and high-reliability applications.
It is difficult to dictate conditions for available current (series resistance) and temperature in a wide variety of applications, so the standard method used to improve reliability in tantalum applications is to derate (reduce) the voltage applied to the capacitor. Industry standards and established design guidelines typically require the designer to derate the voltage of SMD tantalum capacitors to 50 % of rated voltage for best results. This derating has the effect of reducing the typical estimated failure rate from around 1% per 1,000 hours to something more in the neighborhood of 5 FIT (failures in time or failures per billion hours) to 15 FIT. So the reliability improvement is very dramatic in scope.
Achieving the 50 % voltage derating guideline has traditionally been difficult with power bus systems that can range from 28 V to 32 V, such as those found in many of todayís avionics applications. These avionics power line conditions are described in MIL-STD-704. With this derating challenge in mind, the Vishay Tantalum Capacitor division has completed an R&D project that has paved the way for higher rated voltage levels, such as 63 WVDC and 75 WVDC, in SMD tantalums. Where as 50 V rated capacitors have caused concern among designers for these +28 V applications, an industry-recognized safe derating figure of 50% can now be achieved by using Vishay's new 63 V and 75 V tantalum capacitors.
TRADITIONAL DIELECTRIC FORMATION METHODS
The published voltage rating of a SMD solid tantalum capacitor primarily depends upon the thickness and integrity of the Ta2O5 dielectric layer. Thicker dielectric layers provide the capacitor with the ability to withstand higher levels of current, voltage, and temperature stress in the application. With traditional dielectric formation techniques in the industry, the 50 V rating for SMD tantalums has represented the upper level of technology. The dielectric is a film of tantalum pentoxide, Ta2O5, formed on the overall surface of the tantalum particles by means of an electrochemical oxidation. This film is very thin, ranging from a few hundred angstroms to a few thousand. The thickness of the dielectric is controlled by the voltage applied during the electrochemical oxidation process. The oxide growth is amorphous, not crystalline.
This property is very important, since the amorphous oxide has the very high electrical resistance needed to perform as a dielectric. The traditional electrochemical dielectric formation process has consisted of a single-step procedure in which a constant voltage is applied to the tantalum anode while submerged in a liquid electrolyte solution. When the tantalum pentoxide dielectric reaches a pre-determined thickness, the dielectric formation process is completed. This simple, single-step process has proved very effective over the years. Formation of thicker oxide film in several steps in order to create the dielectric for 50 V rated capacitors has also been well known. But the need for 50 V SMD tantalums that will withstand the high mounting temperatures of lead-free reflow processes (typically +260 °C) and the stress of today's high-demand circuit applications calls for a new level of technology
There were three main areas of the traditional dielectric formation process that R&D engineers examined to achieve a better dielectric layer. The resulting dielectric is thicker and more consistent, which results in voltage ratings of up to 75 V for SMD solid tantalum capacitors.
Mechanical stress relief during the formation process.
Local overheating of the electrolyte solution during the formation process.
FORMATION VOLTAGE (DIELECTRIC THICKNESS)
Consistent concentration and purity of the electrolyte during dielectric formation.
With the goal of reducing crystallization of the Ta2O5 dielectric layer (Fig. 1) during the formation process, a multi-step process was developed.
Vishay developed a proprietary, multi-step process that addresses the traditional problems of dielectric formation. Although the specific time segments, temperature profile, applied voltage profile, and electrolyte conditioning methods cannot be divulged in this paper, suffice it to say that areas of concern in the traditional dielectric formation process were addressed successfully and a thicker, more consistent dielectric layer with greatly reduced levels of crystallization has been achieved.
To produce a capacitor design which will meet the requirements of military and high-reliability circuitry, the traditional rule was that the dielectric should be formed to a voltage which is at least 3X that of the rated voltage of the capacitor. So for a 10 V rated tantalum capacitor, the dielectric thickness had typically been formed with an applied voltage in the formation process of approximately 30 V (see Fig. 2). This design rule yields a solid tantalum capacitor which will meet or exceed military requirements. However, as the rated voltage of the capacitor is increased to the 50 V or higher level, and since energy stored is the square of the voltage, a ratio of 4X formation voltage to rated voltage is desirable for optimum reliability under a variety of stress conditions. The new Vishay dielectric formation process allows for formation voltages of 4X the rated voltage, but with a dielectric that is not only thicker, but also remarkably free of crystallization defects for improved reliability and stability over time in the application.
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e working with 28 V or greater are usually compromises at best. It is within this voltage range that traditional SMD tantalum technology with a 50% voltage derating requirement is pushed to its maximum limits. This is especially true where high current levels are available and extreme thermal cycling and high ripple currents can have adverse effects on capacitor reliability.
Alternative technologies to SMD solid tantalums at these voltage levels have comprised the following:
Aluminum Electrolytics - The well-known wear-out mechanism of electrolyte loss is problematic for military electronics, which are typically designed for a useful life of 20 years or more. Lack of availability of SMD packages for large capacitance values and dramatic ESR (equivalent series resistance) increases at low operating temperatures (due to increased resistivity of the liquid/gelled electrolyte) is problems that need to be dealt with in this technology.
Stacked Ceramics - This technology offers very low ESR and DC leakage, but the stacked ceramics exhibit significant capacitance changes with temperature and voltage. Their large size and propensity for cracking is a concern in applications that exhibit high thermal or mechanical shock either in the mounting process or in the application environment.
Polymer Tantalums and Aluminums - Polymer tantalums and aluminums offer low ESR, but stability over the operating life (ESR can increase up to 2X over life), susceptibility to moisture (MSL > 3), and high DC Leakage (up to 10X solid tantalum) limit their applicability. Also, polymer capacitors have a limited field history in high-reliability and military applications. Concerns about the radiation effects on the polymer material make them questionable for space applications.
Solid Tantalum performance characteristics include:
- Over 50 years of field usage in high-reliability and military applications
- No shelf life limitations, wear-out mechanisms, or end-of-life degradation
- Extremely stable ESR, capacitance, and DCL performance over temperature, voltage, and time (see Figures 3, 4 and 5)
- DC leakage is stable through the mounting process, even after three reflows at + 260 °C peak temperatures Fig. 6).
Leakage Failure Mode in Solid Tantalum Chip Capacitors - F. Brindel, J. Fresia, M.McDonald, Vishay Sprague 1998.
MIL-HDBK-217 rev F, DSCC, Columbus, OH
MIL-STD-704, DSCC, Columbus, OH
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