The California Energy Commission’s Public Interest Energy Research (PIER) program and the U.S. Environmental Protection Agency ENERGY STAR program are sponsoring a free one-day technical workshop tomorrow, January 19, to discuss the final draft (Draft 5) of a generalized energy-efficiency test procedure for internal power supplies. This meeting, hosted by ON Semiconductor at its Phoenix headquarters, will be the last forum for concerned parties to comment publicly before the test procedure is finalized. The completed test procedure will be unveiled March 23, 2006, at the Applied Power Electronics Conference and Exposition (APEC) in Dallas.
PIER-funded research conducted in 2003 identified internal power supplies as a significant energy savings opportunity. In the United States alone, modest efficiency improvements have the potential for an estimated 37.3 billion kWh annual electricity savings. However, to date, no test procedure has existed to fairly and consistently measure the energy efficiency of internal power supplies.
The need for standard, accurate reporting of energy-efficiency levels continues to increase as energy-efficiency claims become an important market differentiator. Another motivation for the standard test procedure is the electric utilities’ interest in funding energy-efficiency programs for products that contain internal power supplies.
As a result, PIER provided funding for Ecos Consulting and EPRI Solutions to develop a standard test procedure that would be applicable across the wide range of products types that use internal, ac-dc power supplies. Familiar examples include computers, televisions, monitors and other electronic appliances.
According to the Draft 5 document, the proposed standard test procedure builds on the efficiency test protocol outlined in Section 4.3 of IEEE Std. 1515-2000, IEEE Recommended Practice for Electronic Power Subsystems: Parameter Definitions, Test Conditions and Test Methods. In addition, the test protocol establishes a consistent loading guideline for ac-dc internal power supplies that often have multiple output voltages. The proposed procedure also addresses power supplies used in redundant configurations.
At tomorrow’s workshop, researchers and industry experts will discuss the key elements of Draft 5, review measured data collected over the last two years and suggest final changes needed to the test procedure. A timeline listing milestones in the development of the test procedure and upcoming deadlines appears below.
Those unable to attend the workshop in person can participate via a live Web cast. For instructions on how to participate, visit www.efficientpowersupplies.org/ips_workshop.html. To obtain a copy of Draft 5 of the test procedure and an official comment form, visit www.efficientpowersupplies.org/ips_workshop.html. Comments on this draft or on results of the workshop should be sent no later than Feb. 15, 2006, to Peter Ostendorp, Ecos Consulting research analyst, at [email protected]
Test Procedure Development History and Upcoming Deadlines
- Feb. 15, 2004: Internal Power Supply Test Procedure Draft 1 released.
- Aug. 1, 2005: Internal Power Supply Test Procedure Draft 5 released.
- Jan. 4, 2006: Pre-workshop comments due (e-mail to [email protected]).
- Jan. 19, 2006: Internal Power Supply Technical Workshop
- Feb. 15, 2006: Deadline to submit final comments on test procedure (e-mail to [email protected]).
- March 15, 2006: Summary of test procedure comments posted on www.EfficientPowerSupplies.org.
- March 23, 2006: Final Internal Power Supply Test Procedure unveiled at APEC 2006.