Power Electronics

Symposium to Map Greater Electronics Miniaturization

Following the success of Tessera's inaugural technology symposium last year, and as part of its longstanding commitment to educate and elevate awareness of advanced semiconductor packaging technologies, Tessera Technologies Inc. announces it will host a half-day symposium focused on achieving greater electronics miniaturization through multi-chip, System-in-Package (SiP) technologies. The symposium will be held during the week of SEMICON West 2004. Presentations will cover a wide range of topics, from lowering the risk of SiP implementation to the benefits of system-level design and integration.

When: Tuesday, July 13, 2004 1:00-5:30 p.m. Reception to follow, 5:30-7:00 p.m.

Where: Hyatt Sainte Claire Hotel Downtown San Jose, Calif.

Who: Speakers will include a number of leading technologists and analysts from companies such as Amkor, Gartner Dataquest, Intel, TechSearch, Tessera and others.

Tessera and Chip Scale Review Magazine have teamed to sponsor this event. As space is limited, those interested in securing a spot at the conference should pre-register no later than July 9th at www.tessera.com, or contact Daryl Larsen, symposium event manager, at 408-952-4364. Pre-registration is requested.

For more information, visit www.tessera.com.

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