In the semiconductor industry, the Calibre product name refers to a comprehensive suite of electronic design automation (EDA) tools developed by Siemens Digital Industries Software. These tools are utilized by semiconductor developers during the design, physical verification and manufacturing of integrated circuits (ICs). The Calibre toolsuite comprises two main verification categories—design and manufacturing. The design side tools, used primarily by IC design companies, outsourced assembly and test (OSAT) companies, and intellectual property (IP) providers, include design rule checking (DRC), circuit and reliability verification, and design for manufacturing (DFM) layout optimization. For foundries and independent device manufacturers (IDMs), the Calibre manufacturing tools include lithography simulation, optical process and mask correction, and yield optimization. All the Calibre tools are built on high-performance engines that are continuously enhanced to provide optimal resource efficiency and time management.
The Calibre design toolsuite has undergone significant advancements by incorporating a shift left approach within the physical verification process flow. By adopting these innovative methodology and tools, design companies can identify potential issues at a much earlier stage in the design process, rather than first identifying problems at the final signoff verification stage. This strategic shift toward early detection and correction ensures that any design flaws or inconsistencies are identified earlier in the process, resulting in a more streamlined design-to-manufacturing workflow.
The Shift Left Concept
The concept of shift left involves moving the design testing phase earlier in the project timeline, where time is depicted as moving from the left (representing the past) to the right (symbolizing the future). Since its inception, the shift left philosophy has been embraced across engineering disciplines and tasks, including IC design and verification.
The IC development process comprises several discrete stages. The general engineering assumption is that any problem at any stage will be 10X more difficult and/or time-consuming to detect, identify, and remediate than if it had been detected in the previous stage. This means a problem detected two stages deeper into the flow will be 10X × 10X = 100X more difficult, and so forth.
Traditional IC design and verification flows are based on the waterfall model, in which the project activities are broken down into linear sequential phases, where each phase depends on the deliverables from the previous one.
The Traditional IC Design and Verification Process
The IC development process may be viewed as having two main facets—the front-end logical design and the back-end physical design. In turn, the physical portion of the design flow starts with layout place-and-route (P&R) or custom design, and ends with physical verification and layout optimization.
The final stage before handing the design over to the semiconductor foundry to be implemented in silicon is known as the signoff. Signoff refers to the final physical verification of the layout and involves many facets, including DRC, layout versus schematic (LVS) verification, electrical rule checking (ERC), and design for manufacturing (DFM) layout optimization.
The checks used in this verification, which are coded by the EDA companies for use with their toolsets, interpret the rule decks each foundry has qualified for the target process node. These rules define the requirements a design must comply with to ensure it can be successfully manufactured. There can be tens of thousands of rules at the more advanced nodes, all of which a design must pass before the foundry will accept the design for manufacturing.
Performing signoff verification is computationally expensive and time-consuming. Any issues caught at the signoff stage typically require time-consuming regressions to an earlier stage to be resolved. Designers attempt to maximize functionality in a design by using all available space, which means finding room in a completed layout to implement corrections can be difficult. Even worse, there’s always a chance that fixing one problem will introduce others, some of which won’t be discovered until the next signoff verification attempt.
A Calibre-Enabled Shift Left IC Design and Verification Process
What does shift left with Calibre mean for IC designers? The Calibre toolsuite is renowned for its role in signoff verification. Most of the world’s semiconductor foundries use Calibre tools when they're developing new process node design rules. Furthermore, most design companies and foundries rely on the Calibre platform for signoff verification. This is the last place they want to discover problems, because returning to earlier stages in the process is resource-intensive, time-consuming, and costly.
Although other EDA companies provide some similar verification and optimization capabilities incorporated in their design and P&R tools, the Calibre shift left solution is the only one to use industry-preferred Calibre rule decks. Developers who use EDA tools from other companies to implement shift left verification and optimization, then perform signoff verification with Calibre tools will likely discover dissimilarities in the results, requiring additional rework before tape-out. These discrepancies occur because every EDA company differs in its interpretation of the design rules and implementation of the corresponding design rule checks.
Summary
As discussed in Shift left with Calibre to optimize IC design flow productivity, design quality, and time to market, bringing advanced IC designs to market faster and achieving the ramp to volume production sooner is compelling many IC design companies to implement shift left strategies in their design and implementation flows.
However, when evaluating and selecting a shift left strategy, design companies must consider all the benefits and disadvantages. While using functionality already included in their design and P&R tools may seem the most practical approach at first, it may not be the best option across the full design enablement flow. When inconsistencies between early verification results and signoff verification occur, the time and cost of correcting and reworking designs may be significant.
Most design companies and foundries rely on the Calibre platform for signoff verification, so it only makes sense to use Calibre-based tools to implement a shift left strategy. The suite of tools offers established and proven shift left solutions, enabling design teams to improve productivity, efficiency and cost savings while realizing the renowned quality associated with the Calibre toolsuite.