Power Electronics

Shootout Volume 5: Paralleling eGaN® FETs – Part 2

In the first installment of this two-part article on paralleling eGaN FETs, five basic designs, utilizing four EPC2001 (100 V, 25 A) paralleled devices per switch in a half bridge configuration were presented with experimental validation. In this second installment, a 1MHz buck converter is demonstrated using two parallel eGaN FETs with exceptional performance compared, with state-of-the-art silicon devices in a similar circuit.

To evaluate the performance difference between paralleled MOSFETs and eGaN FETs, an asynchronous buck converter was built and tested. The basic schematic of the converter is shown in Fig. 1. The buck converter was designed with an input voltage up to 19 VDC and an output of 1.2 V. The circuit uses the Linear Technology Buck Regulator LTC3833 IC [3] for both designs. The National Semiconductor LM5113 eGaN driver [4] was added for the eGaN FET version of the converter to provide gate drive compatibility.

Two variations in the layout design of the eGaN version buck converter were made and are shown in Fig. 2. The variations are a single FET version and dual paralleled FET version, the paralleled device being the synchronous rectifier. The layout of the paralleled version was based on evaluation design E from reference [8]. (The best theoretical design discussed in this reference, “Design B”, was not selected for this evaluation because, at the time of the design, we did not realize its superior attributes).

Fig. 3. shows photos of the buck converters built for the comparative evaluations. The eGaN FET boards are approximately 2 x 2 in. and the yellow dotted line indicates the footprint area of the converter itself.

The MOSFET version of the synchronous buck converter was evaluated using the Linear Technology demo board DC1640A [2]. The converters’ design summaries are given in Table 1.

The inductance values given in Table 1 are only for the synchronous rectifier FET as it was these devices that were paralleled in the dual FET versions. By measuring oscillation frequency of the gate voltage at the gate of the devices, using specially designed probes embedded within the PCB, and having low gate driver resistances (< 0.5 Ω), the gate inductance could be calculated from the first order resonance equation using the value of the gate-source capacitance. Using the dimensions between the two device sources, the inter-device source inductance could be calculated using the flat conductor inductance formula [9]. The length of the inductor was given as the distance between two source pads closest to each other and the width of the conductor as the width to the via sets. The thickness was given as the conductor thickness.

Both converters were operated at a switching frequency of 1 MHz and with 12 Vdc on the input. The MOSFETs [6,7] selected were based on physical fit into the demo board and having a similar gate threshold voltage as the eGaN FETs [5]. All the converters were built using the same output inductor, a Wurth 744308025 250 nH, 370 µΩ and four paralleled 100 µF ceramic 1206 size output capacitors.

Fig. 4. shows the efficiency measurement results for each of the converters over a wide load current range. The results clearly show the superior efficiency performance of the eGaN FET based converter over the MOSFET equivalent. This efficiency improvement is despite the near double RDSon value the eGaN FET when compared to the MOSFET. The MOSFET version efficiency is further negatively affected by the 30 ns of body diode conduction inherent in the controller.

The switching voltage node waveforms for each of the Buck Converters were measured and shown in Fig. 5 and Fig. 6 for the single device and dual device converters respectively.

The dv/dt for each of the converters was also measured and the results given in Table 2. It must be noted that in the dual eGaN FET case, the dv/dt is higher than predicted for immunity [8]. The fact that the measured dv/dt is higher than the predicted immunity does not indicate that any parameter of the eGaN FET is exceeded. The gate can experience a negative voltage spike during turn-off that can artificially improve the miller capacitance ratio. The designer must measure and look for signs of unwanted turn-on on the waveforms. One of these signs may be a small bump during the transition period on the drain-source voltage.

It should be noted that paralleling of FETs for the synchronous rectifier switch of a Buck Converter is a special case as noted in [1]. This case has favorable conditions for the FET making it much less susceptible to source inductance than in the case of other types of converters and switches. Reference [1] goes as far as to indicate that increased source inductance up to a point may even be beneficial.

Paralleling eGaN FETs

Summarizing the previous experiments, general design rules for paralleling eGaN FETs are:

  • Keep the source inductance between devices as low as possible in the design. This inductance is not to be confused with the common source inductance for a single device. This can be achieved by short wide structures.
  • Keep all the gate connections very tight with respect to each other. The smaller the “open” distance between gate connections, the smaller the common source inductance.
  • Keep the gate source impedance as low as possible and, in particular, the inductance. This is difficult to achieve since the gate connections are typically long narrow traces. Since trace width is generally constrained, the design must keep the gate trace as short as possible.
  • Drain inductance may be increased with respect to source inductance. It has been shown that drain inductance may aid in keeping the system stable over a wider range of operating conditions. Too much inductance is also detrimental. Physically this means that a group of switches may be spread apart slightly when designing the layout.
  • Reduce the dv/dt of the switching event by increasing the gate driver source resistance. This will help damp out oscillations that can occur in the gate loop which otherwise can lead to exceeding the maximum allowed gate voltage.
  • Add gate turn-off resistance to help damp the gate circuit. As in the case for the turn-on, the turn-off may oscillate during a switching event. In the case for turn-off, the gate can ring negative or positive. A positive ringing can lead to unwanted turn-on of the switch.

Conclusion

Can eGaN FETs be connected in parallel? Yes! However, it must be noted that paralleling eGaN FETs may require adjustment to the gate circuit to reduce the switching speed and ensure operation within the immunity limits of the device. Adjustment to the switching speed can be achieved by changing the values of the turn-on and turn-off resistances in the gate driver.

Furthermore, there are special cases that improve converter operation when using paralleled devices. One such example is the synchronous rectifier in a buck converter where increased dv/dt immunity can be achieved by adjusting the dead-time to zero between the active devices and allowing a negative voltage overshoot on the gate.

In Part 2 of this two-part study, the lessons about circuit layout from Part 1 were applied to an actual buck converter operating at 1 MHz. It was shown that connecting two eGaN FETs in parallel can yield converter performance on par with single device equivalents, and far better than can be achieved with state-of-the-art silicon MOSFETs.

References

  1. “Effect and Utilization of Common Source Inductance in Synchronous Rectification,” Bo Yang, Jason Zhang, Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, March 2005, Vol. 3, pp 1407 - 1411
  2. “LTC3833EUDC High Efficiency Step-Down DC/DC Converter,” Linear Technology Demo Manual DC1640A, document dc1640af.pdf
  3. “Fast Accurate Step-Down DC/DC Controller with Differential Output Sensing,” Linear Technology datasheet LTC3833
  4. “5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs,” National Semiconductor datasheet for LM5113
  5. “EPC1007--Enhancement Mode Power Transistor,” Efficient Power Conversion datasheet for EPC1007
  6. “OptiMOS™ 3 M-Series Power-MOSFET,” Infineon Technologies AG datasheet for BSZ130N03MS G
  7. “OptiMOS™ 3 M-Series Power-MOSFET,” Infineon Technologies AG datasheet for BSZ035N03MS G
  8. “Shootout Volume 5: Paralleling eGaN FETs,”,Part 1, Power Electronics Technology, September 2011
  9. http://chemandy.com/calculators/flat-wire-inductor-calculator.htm

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Table 1: Summary of MOSFET and eGaN FET converter design characteristics
Single FET Design Dual FET Design
eGaN EPC1007/ EPC2001 EPC2001/ 2x EPC2001
MOSFET BSZ130N03MS / BSZ035N03MS BSZ035N03MS / 2x BSZ035N03MS
Gate inductance eGaN FET 3.2 nH 6.8 nH
Gate inductance MOSFET 10.4 nH 12.8 nH
Source inductance eGaN FET 120 pH 286 pH
Source inductance MOSFET 1317 pH* 1103 pH*
di/dt limit eGaN [A·ns-1] 17.7 7.4
di/dt limit MOSFET [A·ns-1] 1.7 2.0
dv/dt limit eGaN [V·ns-1] 11.5 5.6
dv/dt limit MOSFET [V·ns-1] 9.7 6.2
* Inductance includes inductance internal to the MOSFET package.
Table 2: Measured dv/dt limits for each of the design examples
Single FET Design Dual FET Design
eGaN FET design measured dv/dt [V·ns-1] 12 10
MOSFET design measured dv/dt [V·ns-1] 2.2 1.16
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