Distributed power systems are prevalent in telecommunications, networking, and high-end server applications and utilize a 48 V bus voltage adopted from the telecom industry. From the 48 V bus, a number of isolated point of load (POL) converters power the end loads, with isolation being required for safety. The traditional distributed power architecture (DPA), Fig. 1(a), uses AC/DC front end converters to deliver the 48 V bus voltage. From the 48 V bus voltage, a number of regulated isolated DC/DC POL converters are used to deliver the required voltage and power to the individual loads. As communications, networking, and high-end server systems have become more complex, the voltages and currents demanded by the growing number of loads have increased significantly . Having a large number of regulated 48 V isolated DC/DC POL converters to power these systems significantly increases the cost, volume, and complexity of the system.
The limitation of the traditional distributed power architecture is that as the power demands of the loads increased so did the complexity of the isolated converters required. Fully regulated isolated POL converters are much larger, more complex, and more expensive than low voltage non-isolated POL converters. The isolated converters introduce a bulky transformer and complex control due to the isolation requirements; this leads to lower efficiency and power density. To simplify design, the concept of intermediate bus architecture (IBA) was considered . A popular IBA approach, shown in Fig. 1(b), employs a lower number of 48 V isolated bus converters that satisfy isolation requirements and supply an intermediate bus voltage ranging from 9.6-12 V. With the final regulation to the loads provided by smaller, more efficient, regulated non-isolated POL converters, the bus converters can be operated as unregulated DC/DC transformers, improving efficiency and reducing cost. The IBA is widely used in many distributed power systems today, yielding improved performance and lower overall system cost when compared to traditional architectures.
The unregulated bus converter, also known as a DCX, or DC/DC transformer, is generally operated close to 50% duty cycle to offer the highest efficiency and power density. The majority of today’s bus converters use traditional hard switching bridge topologies operating at lower frequencies to maximize efficiency. At lower switching frequencies, the isolation transformer and output inductor are very bulky, occupying a large portion of the board area. In an effort to improve power density, the operating frequency can be increased to shrink the inductor and transformer size . As frequency is increased in traditional hard switching topologies, the losses from body diode conduction, reverse recovery, and switching increase significantly, limiting the converters output power capability.
Resonant Bus Converter
To offer improved efficiency at higher switching frequencies, resonant topologies may be considered. Resonant topologies- are particularly beneficial in DC/DC transformer applications, due to the removal of the regulation requirement, allowing the converter to always operate at the resonant frequency. For this work, the benefits of the eGaN FET applied in a high frequency intermediate bus converter (IBC) will be considered. The topology, shown in Fig. 2, employs a resonant technique that utilizes the transformer’s magnetizing inductance (LM) and resonance of the leakage inductance (LK), with a small output capacitance (CO), to achieve zero voltage switching (ZVS), limit turn off current, and eliminate body diode conduction .
To obtain a direct comparison in performance between eGaN FETs and Si MOSFETs in the high frequency resonant bus converter application, devices with similar on-resistance were selected, the same circuit topology was used, and a similar layout was maintained for the eGaN FET and MOSFET designs. Direct comparisons of the key parameters for the eGaN FETs and Si MOSFETs are shown in Table 1 and Table 2. The Figures of Merit (FOMs) used in this work are QG x RDS(ON) and QOSS x RDS(ON). These particular FOMs were selected due to the soft switching topology that reduces the switching related losses, therefore resulting in the FET gate drive and conduction being the major loss contributors.
Device output charge has a direct impact on the energy required to achieve ZVS. A reduction in energy required to achieve ZVS can result in reduced dead time, providing a larger power delivery period (t0-t1 in Fig. 2(b)) and lower RMS currents in a high frequency resonant converter. The eGaN FETs show significant improvements when compared to Si MOSFETs, with the gate drive FOM improving by a factor of approximately 4 and 3 for the 100 V and 40 V devices respectively, while the output charge FOM is improved around a factor of 1.6 and 2 for the primary and secondary devices respectively. The eGaN FET also provides performance improvements in the form of reduced miller charge that reduces the turn off switching losses incurred in the primary devices. As a further advantage, the LGA packaging of the eGaN FET has low parasitic package inductance compared to the traditional Si MOSFET package (SuperSO-8). When putting all these benefits together, multi-MHz switching frequencies can be obtained through the use of advanced topologies combined with low loss eGaN FETs
To compare the performance of eGaN FETs and Si MOSFETs in high frequency resonant converters, two experimental prototypes, shown in Fig. 3, were designed and tested based on the schematic in Fig. 2(a). To accurately compare only device performance, these prototypes both had the same 3F45 Mn-Zn transformer core and identical windings designed from . The placement of the primary side input capacitors and secondary resonant capacitors were similar for both designs to ensure similar parasitic inductances for the primary and secondary loops, with the only differences being those introduced by the different packages of the Si MOSFETs and eGaN FETs. By using eGaN FETs with lower specific RDS(ON) and improved packaging, the active footprint area shrank significantly, reducing the power stage size by 30% compared to the Si MOSFET benchmark design. The eGaN FET–based design used LM5113 drivers from Texas Instruments for the primary and secondary devices, driving the devices at 5 V. The Si MOSFET–based design used drivers comparable in performance to the LM5113 with an 8 V drive for the primary and a 5 V drive for the secondary to provide improved high frequency Si MOSFET performance, by reducing dominant gate losses for a small penalty in the on state resistance. For both designs, the gate drives were placed on the backside of the board. The generation of these driver chip voltages from the nominal 48 V input are not included in this work, but the gate drive losses incurred in the switches are considered.
The experimental switching waveforms for the designs at 1.2 MHz are shown in Fig. 4 and Fig. 5. Both designs have the same magnetizing inductance, built into the transformer via an air gap, to achieve zero voltage switching during device off state (t1-t2 in Fig. 2(b)). Due to almost a factor of 2 decrease in output charge (QOSS) provided by the primary and secondary eGaN FETs, the ZVS transition is achieved in a proportionally shorter period, increasing the effective duty cycle and improving the overall converter performance. For the Si MOSFET design, the dead time required for ZVS was measured to be 87 ns and the effective duty cycle for each device was limited to 34%. With the faster switching eGaN FETs the dead time was reduced to 42 ns, resulting in a 42% duty cycle for each device, allowing for an increased power delivery period. From the switching waveforms, it can also be seen that the gate drive speed for the eGaN FET is significantly faster than the Si MOSFET counterpart even when driven with a lower gate drive voltage, providing both faster switching speed and reduced gate losses.
Efficiency vs. Power Loss
The comparison in efficiency and power loss between the two designs operating at 1.2 MHz is shown in Fig. 6. The eGaN FET based converter offers a one-percentage point improvement in peak efficiency over its Si MOSFET counterpart, resulting in about a 25% decrease in power loss. Since brick designs are thermally limited by a given full load loss based on the size of the converter, the reduction in power loss translates directly into higher output power handling capability. The eGaN FET converter can increase the output power capability by up to 65 W, while maintaining the same total converter loss when compared to the benchmark Si MOSFET design. Assuming around a 12 W maximum power loss for both designs, the output power of the eGaN FET based converter increases from 270 W to 325 W.
The loss breakdown for the 1.2 MHz designs at output currents of 2.5 A and 20 A is shown in Fig. 7 and leads to the conclusion that the eGaN FET reduces gate drive losses and improves efficiency for all load conditions. At high currents, the conduction loss dominates total power loss, but the eGaN FET converter’s shorter ZVS dead time provides reduced conduction losses due to lower RMS currents, which are inversely proportional to the effective duty cycle. Another impact of the reduced ZVS time on the eGaN FET converter is an increase in transformer core loss, which is a result of the higher transformer flux density generated from an increase in the duration of the power transferring period. The increase in transformer core loss is much smaller than the reduction in conduction losses at high current, leading to larger power savings at high currents for the eGaN design.
From the results at 1.2 MHz, it can be seen that the Si MOSFET converter is approaching its frequency limit – i.e. the ZVS transition time is becoming a significant portion of the overall period, while the eGaN FET has the capability to further increase switching frequency. To compare the frequency improvements possible with eGaN FETs over Si MOSFETs, the converter’s operating frequency was reduced to 800 kHz for the Si MOSFET design and the eGaN design was increased to 1.6 MHz. For both of these designs, the core structure remained the same and was not optimized for the different operating frequencies. The efficiency and loss comparisons between the designs are shown in Fig. 8, with the eGaN FET design offering a 0.9% peak efficiency improvement and lower power loss up to an output current of 29 A. The sharp drop off in efficiency at currents above 20 A for the eGaN FET based converter is a result of the increased AC transformer winding losses and reduced effective duty cycle incurred at the high frequency. Conversely, the flattening out of the efficiency for the 800 kHz Si MOSFET design was a result of the reduced AC transformer winding losses and higher effective duty cycle at the lower frequency.
This research demonstrated that eGaN FETs can also provide significant improvements in the performance of soft switching/resonant converters when compared to Si MOSFETs. In high frequency applications, the reduction in:
- Output capacitance can decrease circulating energy and commutation time required to achieve ZVS, thus increasing the effective power delivery intervals and improving overall efficiency.
- Gate capacitance provided by the eGaN FETs results in faster switching speeds, at reduced driving voltages, which provide reduced gate drive losses. Putting eGaN FETs to work in high frequency applications can help push the frequency, without sacrificing converter performance.
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