Although electromechanical relays have historically been the primary load switch in most applications, MOSFETs have been encroaching on the relay's territory in recent years as technology advances MOSFET on-resistance closer to that of an ideal switch (in which case RDS(ON) = 0Ω ). However, MOSFET on-resistance still remains greater than that of an equivalent electromechanical relay. As a result, thermal considerations need to be taken into account when designing with MOSFETs.
Thermal factors become especially important when switching into a capacitive load. The resulting inrush current can be large enough (about 10 times greater than the steady-state current) to cause the MOSFET's junction temperature to exceed its maximum rating. This is where simulation can be very useful in predicting the junction temperature over a host of electrical and environmental conditions.
There are several ways to make MOSFET junction temperature estimates, but most rely on a fixed equation set that must be rewritten whenever the circuit topology changes. Furthermore, most techniques do not account for interaction between the electrical and thermal aspects of the circuit system. However, a simulation method using a quasi-dynamic MOSFET model allows for efficiently analyzing different topologies, while also accounting for electrothermal interactions.
Electromechanical vs. Solid-State Switches
The benefits of using MOSFETs over relays are that they do not exhibit contact wear, they can be controlled by a low-current, low-power drive circuit, they can be controlled with a PWM scheme to reduce inrush current, and they can be placed on the same pc board as the control circuitry in high-current applications.
Nevertheless, relays have contact resistances of below 1 mΩ, whereas MOSFETs have on resistances ranging from a few milliohms to hundreds of milliohms, depending on their voltage rating and technology. Thus, relays can handle large inrush currents when driving a capacitive load. In addition, a single MOSFET cannot be used as a bidirectional switch because it can conduct in the negative direction through the body diode in the off-state. To accommodate bidirectional operation, two back-to-back MOSFETs configured in reverse series are used to create a bidirectional switch. Fig. 1 illustrates both a bidirectional switch configuration and a high-side dc switch configuration.
Estimating MOSFET Junction Temperatures
For a given circuit topology, there are power-estimation techniques used to determine power dissipation in a semiconductor device. The most commonly used power-estimation equation is:
P = I × V × D, Eq. 1
where I is the average current during the conduction cycle, V is the equivalent voltage across the device during the conduction cycle, and D is the duty cycle
In the actual circuit, the parameter I is a function of circuit operation. The parameter V is a function of multiple parameters, including the parameter I, the semiconductor type, the die-junction temperature and the device-control method. To apply this equation to a diode, V = VD, where VD is a function of both IDIODE and temperature. For a MOSFET (in the on-state), VDS = IDS × RDS(ON). RDS(ON) is a function of IDS, VG and device temperature. For an IGBT in the on state, V = VCE(SAT), where VCE(SAT) is a function of ICE, VG and device temperature. In order to determine the junction-temperature rise of the semiconductor, the power is simply multiplied by the thermal impedance. The problem with this type of analysis is that it oversimplifies the power calculation and does not take into account transient conditions, such as switching events or dynamic circuit operations.
To determine a transient junction temperature rise using the simplistic power model, a rectangular power pulse P for duration t with duty cycle D is assumed. P is multiplied by the value of the combined thermal impedance presented by all relevant power-dissipation paths for the given duration of the pulse.
Fig. 2 shows the thermal impedance curve of a MOSFET based on a dynamic model that includes thermal capacitance. The x-axis represents the pulse duration t. The y-axis represents the thermal impedance between the junction and case of the MOSFET. The graph shows a family of thermal impedance curves for different values of D. Multiplying P by the corresponding value for thermal impedance (θ) yields the amount by which the junction temperature will rise above the case temperature.
The problem with this junction temperature estimate is that if the thermal impedance curve is given from junction to case, as it is for the TO-220 and TO-247 packages, the case-to-ambient temperature rise has not been taken into account. It is not sufficient to just assume the case is held at TAMBIENT. Fig. 3 shows a physical rendition of the thermal system for a MOSFET.
Simulating MOSFET Junction Temperatures
Circuit simulation uses complex component models along with network analysis, which renders a closer approximation to the actual operating condition of each device in the circuit. Thus, the simulator will automatically calculate the power dissipation of the device, taking into account gate driving, switching transitions and diode reverse-recovery phenomenon as the component of interest is operating in a circuit. Traditional circuit simulation performs power calculations based on a static thermal model in which certain aspects of the component do not change as the part heats up. There are no changes to the model performance as a function of temperature. This is adequate when performing circuit simulation at the IC level, where self-heating is insignificant. Power semiconductors do self-heat, however, because they consume power on the order of watts, whereas transistors and diodes at the IC level consume only milliwatts or microwatts. To get around the limitation of semi-conductor component models exhibiting only static thermal behavior, a quasi-dynamic thermal “wrapper” model is added to the 25°C thermally static model.
Spice is the defacto standard simulator in electrical engineering; however, there are a number of non-Spice based simulators that support hardware description languages. The quasi-dynamic wrapper (Fig. 4) can be added to the static model in several ways. If Spice is used, macro-modeling techniques can be used. If a simulator such as Simplorer, Saber or Spector is used, their respective hardware description languages can be used to implement the equations directly. Alternatively, all simulators can use the macro modeling method, which is the easiest to implement but has some limitations, depending on the macro modeling capability of the simulator. The rest of the discussion will focus of the macro modeling approach using a MOSFET as an example.
Thermally Dynamic MOSFET Model
There are two temperature-dependant MOSFET parameters that can be implemented using the “wrapper” approach. They are the values for the threshold voltage (VTH), and RDS(ON) when the MOSFET in fully enhanced (i.e. in the on state).
The threshold voltage increases at the rate of approximately -7 mV/°C. RDS(ON) has amild quadratic relationship with temperature. Mathematically, these relationships are easily represented; however, obtaining the temperature from these relationships in a simulation can be challenging.
The thermal network is usually a ladder type comprised of thermal resistances and capacitances whose step response resembles the single-pulse curve in Fig. 2. Fig. 2 also shows this thermal RC-ladder network, and such networks are included in the thermal datasheets for most new MOSFETs. Older MOSFET datasheets omit the ladder network, though it can be synthesized from the single-pulse curve.
The first item that needs to be obtained for the network model is the RDS(ON)-vs.-TJ relationship. All MOSFET datasheets include an RDS(ON)-vs.-TJ curve, and there are routines available that will fit three points from the curve, such as that in Fig. 5, to a quadratic equation. For example, a simple quadratic curve-fitting routine can use the RDS(ON)-vs.-TJ curve to evaluate the coefficients for the following equation:
RDS(ON)(TJ) = RDS(ON)(25°C) × [a × TJ2 + b × TJ + c], Eq. 2
where a, b and c are the curve-fitting coefficients that yield the curve in Fig. 5. Once the coefficients for Eq. 2 have been obtained, then dRDS(ON)(TJ)/d TJ can be derived with the following formula:
Eq. 3 gives the RDS(ON) variation as a function of TJ. In Eq. 3, dTJ is ΔTJ = (TJ - 25°C). Given that the MOSFET model assumes no self-heating, the value for TJ of the MOSFET is held constant at 25°C when solving its constituent equations. Therefore, dRDS(ON) adds to or subtracts from the effectively solved RDS(ON), giving a self-heating effect. So, dRDS(ON) is:
dRDS(ON) = RDS(ON) (25°C) × (2 × a × TJ + b) × (TJ — 25°C).
In Eq. 4, RDS(ON)(25°C) = VDS/ID is solved by the simulator using the Spice model. The next step is to determine TJ in Eq. 4. This requires that the instantaneous power in the MOSFET is calculated according to the following equation:
P = ID × VDS. Eq. 5
Here switching losses due to the MOSFET's gate resistance (RG) are neglected. The power calculated in Eq. 5 is imposed on the thermal network inset in Fig. 2. For Spice simulators, power is analogous to current and temperature is analogous to voltage. Thus, a power-/current-source drives the thermal network.
In the lower portion of Fig. 6, note the absolute value block. This is required because power dissipation is always adding heat to the system, never removing heat. TJ is the temperature/voltage at the power/current source node. Finally, the temperature dependence of the threshold voltage is added. Temperature of the threshold voltage VTH is characterized as a simple linear relationship:
VTH(TJ) = -0.007 × (TJ — 25°C). Eq. 6
In Eq. 6, TJ -25°C accounts for the Spice model being characterized at 25°C. Now that the characterizing equations have been derived, they have to be put together to create the model. This can be accomplished with the following steps:
First, obtain the datasheet for the MOSFET. Second, obtain the 25°C Spice model for the MOSFET. Third, obtain the thermal network model for the MOSFET (newer MOSFET datasheets include the thermal networks). Fourth, obtain the coefficients for the temperature-dependant RDS(ON) curve. Fifth, implement the macro model, including Eqs. 4, 5 and 6, and the upper portion of Fig. 6. Note that in the upper portion of Fig. 6, VTH from Eq. 6 is the value of the voltage source placed in series with the gate of the MOSFET.
The “if-else” statements in Fig. 6 account for the state of the MOSFET during simulation. If VDS is greater than 100 mV, a 1-µΩ resistance is added to the channel. If VDS is less than 100 mV, then the MOSFET is assumed to be in the on state, and the temperature dependent dRDS(ON) is added. TAMBIENT is the ambient temperature of the case. In this model, the case is held to TAMBIENT; however, it is easy to expand the thermal network to include a heatsink effect on the system.
Modeling Example: High-Side Switch
A high-side switch driving a capacitive load is a good example of how this type of dynamic electrothermal modeling can be useful in choosing, driving and heatsinking a MOSFET in power-switching applications. In this example, the load is a power supply with large input capacitors.
Fig. 7 shows a behavioral model of the PVI1050N photovoltaic isolator, which is being controlled by an equivalent of an open-collector/drain transistor. STATE1, STATE2 and TRANS1 trigger and control the switch S1. C1 and R2 mimic the pc board's loading. R2 results in a 10.8-A steady-state load, while C1 represents the bulk capacitors of the power supply. IGATE, VGS and PWR_FET are current, voltage and power probes. The IRFP4232 is a quasi-dynamic MOSFET model that has been constructed in the manner outlined in the previous section. The heatsink shown connected to the MOSFET is a single TO-247 heatsink modeled as a thermal impedance of 4.7°C/W. The thermal capacitance of the case-to-ambient thermal pathway through the heatsink is neglected because it is large compared to the thermal capacitances of the package. As such, it will not contribute much to the fast transient power-pulse-induced temperature rise.
In Fig. 8, the non-standard current-overshoot waveform — between when the current starts flowing and after the MOSFET is fully enhanced — is caused by the slow rise of the gate voltage VG. Fig. 8 shows the slow rising of VG, which is caused by the low drive-current capability of the PVI1050N.
The charging of the Miller capacitance of the MOSFET causes the gate-voltage plateau in Fig. 8, known as the Miller plateau. During this time, the MOSFET is being driven near the threshold of conduction, which results in the MOSFET operating in the linear region. Operating in the linear region causes high power dissipation because both IDRAIN and VDS are relatively high during that time. The power spike in Fig. 8 illustrates the high power associated with the MOSFET operating temporarily in the linear region.
The peak junction temperature in Fig. 8 is 139°C, with a temperature rise of 114°C above the 25°C ambient. Since the network that represents the MOSFET's package and heatsink is linear, it can be expected that the junction rise would be 114°C, regardless of the starting ambient temperature. This is because the MOSFET model does not have any thermal effects built-in for the linear region of operation. However, since the duration of time that the device is in the linear region is fairly short compared to the overall system's time constant, there is only minor a non-linearity that is not taken into account.
If the package was surface-mounted using thermal vias or a large copper plane, then the only way to get a reasonable thermal model of the case-to-ambient network would be to use a software package that can generate the network from geometric and material information.
For any given circuit that can be simulated statically, a quasi-dynamic model can be created to add the self-heating effect. It should be noted that the simulation assumes that the MOSFET and heatsink are thermally isolated from all other heat sources on the same board. The largest benefit of simulating with a quasi-dynamic model is that it allows for straightforward analysis of different circuit topologies without oversimplifying the problem to fit a fixed equation set. Nor will the equations have to be rewritten if the circuit topology is taken into account. This methodology is effectively virtual prototyping. Once the model is created it can be put into a library and be used by simply drawing a new design.