Power Electronics

Protecting MOSFETs Against Overcurrent Events

While response time is a key metric of overcurrent protection effectiveness, it must be translated into peak MOSFET current and power loss to provide a true measure of robustness.

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Protecting power transistors against overcurrent failure has always been a challenging issue in power circuit design. In order to protect against even the most potentially destructive overcurrent events, it is critical to quickly initiate a shutdown of a power transistor. While fast response time in overcurrent protection circuits is generally considered optimal, the implications on reliability are neither broadly understood nor readily quantified within the power electronics design industry. For example, most designers would agree a protection circuit that has a response time of 3 µs instead of 5 µs improves the protection quality. But, the improvement is difficult to quantify in an objective measure of design margin or in terms of any characteristic besides response time.

Even when fast response time becomes the design focus of the protection scheme, the objective is not easy to meet. When an analog current-sensing technique is employed, the signal must be converted into a digital overcurrent signal. While this is straightforward, the conversion can easily be corrupted by noise in a power-switching environment. Filtering solves this problem but has a negative impact of slowing the response time. As always, size and cost are also important considerations. A sensing technique with marginal performance is often substituted to provide a faster solution to meet cost and size constraints, and provide the correct perceived value for the application.

The issue of response time for power MOSFET protection is particularly relevant in many power supply applications and can be addressed in various ways. One technique proposed here achieves fast response time while meeting cost and size constraints. To study the MOSFET losses during an overcurrent event, a simple model for a current waveform can be applied. This model provides a straightforward means to determine the impact of response time on MOSFET loss components and, in turn, the ability to characterize the benefits of faster response time in design margin terms of transistor losses and peak operating current.

The protection technique proposed here is included in a test circuit. The circuit has a MOSFET switching into a short circuit producing fast-rising overcurrent events. The protection scheme uses a small, integrated, overcurrent detector (OCD) to provide a fast-acting, noise-immune overcurrent signal. This signal ensures fast MOSFET shutdown and robust protection. The circuit, which allows the protection response time to be varied, will be used to examine transistor waveforms for different response times.

Many of the concepts relating to the protection of power MOSFETs can be applied to other power transistor types such as IGBTs. Understanding overcurrent protection in general provides designers with a tool to quantify the margin in their protection schemes, and in the end improves design reliability for all power transistor applications.

Waveform Model

The model for an overcurrent waveform is shown in Fig. 1. This waveform is divided into six periods based on the state of operation of the MOSFET, the drain current relative to the current limit threshold and the output state of the protection circuit. Table 1 describes current, voltage and protection circuit assumptions for each period. These simplifying assumptions make it straightforward to write equations for voltage, current and power, and integrate the power equation to determine the energy dissipated in the MOSFET. The series of equations developed for the On period is as follows:

Table 1. Overcurrent waveform periods and the simplifying assumptions used in the spreadsheet model.
Period Description Voltage and Current Assumptions
Turn On
(t0 < t < t1)
MOSFET transitioning from off state through linear region to saturation region. Drain-to-source voltage ramps down from Drain current ramps up from zero to
On
(t1 < t < t2)
MOSFET operating in saturation region. Drain current hits limit at end of period, but overcurrent not detected. Current rising at a fixed rate. Voltage equal to ID(t) × RDS(ON).
On-OCL
(t2 < t < t3)
MOSFET operating in saturation region. Current over limit throughout period, but overcurrent not detected until end of period. Current rising at a fixed rate. Voltage equal to ID(t) × RDS(ON).
On-OCD
(t3 < t < t4)
MOSFET operating in saturation region, but logic and gate-drive transitioning to start discharging Miller capacitance at end of period. Current over limit and detected throughout period. Current rising at a fixed rate. Voltage equal to ID(t) × RDS(ON).
Turn Off
(t4 < t < t5)
MOSFET transitioning from saturation region through linear region to Avalanche. Voltage rises at a fixed rate to VBRdss. Current stays fixed at
Avalanche
(t5 < t < t6)
MOSFET in Avalanche. Voltage stays fixed at VBRdss. Current ramps down to zero at a fixed rate.


where It1 equals the current at the end of the Turn On period; k2 equals the rate of current rise; RDS(ON) equals MOSFET on-resistance at the junction operating temperature; P2AVG equals the average power dissipation contributed by On period energy losses in a repetitive pulse-by-pulse, current-limit mode; and f equals the frequency of the pulse-by-pulse current limit.

Although these equations are long, they are simple to solve. Moreover, it's easy to define the time ending the ith period, ti, based on setting current rise rates, ki, circuit operating voltages and currents, and component data sheet parameters. Equations for all six periods were developed using this same process. This set of equations was then added to a spreadsheet.[1]

To fully specify the equations, values for ti, ki, I and must be specified or calculated. Specification is based on either circuit operating conditions — operating voltage and worst-case current rise rates — or component specifications — MOSFET switching times, MOSFET on-state resistance and current detector response time. For this simulation, data sheet parameters for an IRFZ48V MOSFET were used. Circuit operating and MOSFET data specifications used for the simulation are shown in Table 2.

Table 2. Spreadsheet model input parameters.
Period Circuit Operating Input Parameters IRFZ48V Input Parameters
Turn On
(t0 < t < t1)
tr = 0.2 µs
On
(t1 < t < t2)
k2 (current rise rate) = 75 A/µs
Is (current limit threshold) = 75 A
RDS(ON) = 24 mΩ at TJ = 150°C
On-OCL
(t2 < t < t3)
k3 (current rise rate) = 75 A/µs
td = 1 µs to 5 µs
RDS(ON) = 24 mΩ at TJ = 150°C
On-OCD
(t3 < t < t4)
k4 (current rise rate) = 0
tl = 0.4 µs
RDS(ON) = 24 mΩ at TJ = 150°C
Turn Off
(t4 < t < t5)
Avalanche
(t5 < t < t6)
EA = 0.5 mJ at 75 A; Model scales energy based on the square of current.


Simulation

Fig. 2 presents the current waveforms for three different detector response times (1 µs, 3 µs and 5 µs). Several observations can be made based on these waveforms. First, the portion of the waveform that occurs before the current exceeds the set limit is the same for all three response times. This is to be expected and leads to the conclusion that the transistor losses in the Turn On and On periods are independent of response time.

Second, the On-OCL period is the first period impacted by the response time. The end of this period is defined by the first knee in the waveform where it transitions to horizontal. This knee is the point at which the overcurrent condition is detected. Slower response times cause higher currents and a longer time duration in this period. With the MOSFET on, energy loss is proportional to the square of current and time, so energy loss in this period will dramatically increase with slower response time.

Another concern is that the On-OCD and Turn Off periods also experience higher currents based on the inherited current from the On-OCL period. But their durations remain unchanged. Therefore, their losses will increase due to higher current, but will not include an addition from a larger time component. The On-OCD loss will increase proportionally to the square of current, and the Turn Off loss will increase in direct proportion to current.

Furthermore, the model calculates avalanche energy based upon a model input of energy at a lower current level. The energy is then scaled based on the square of the ratio of the current at the beginning of the Avalanche period to the current at which the avalanche energy was specified. In this case, the higher current inherited from the On-OCL period will increase the avalanche energy dramatically as well as the duration of the Avalanche period.

A final observation is that the peak current increases significantly for increasing response times. The simulation provides a peak current of 300 A and 450 A for response times of 3 µs and 5 µs, respectively. Both of these values exceed the IRFZ48V's absolute maximum pulsed drain current rating of 290 A.[2] So, in this case, a 3-µs response time would not be adequate to ensure the MOSFET was operating in its safe operating area.

This same model is used to calculate the MOSFET energy loss. Fig. 3 shows the energy loss for each period of the waveform with different detector response times. The plots show a dramatic increase in total energy loss, 3.7 mJ to 14.1 mJ, as response time is increased from 1 µs to 3 µs.

This increase is driven primarily by losses generated in the On-OCL and Avalanche periods. This fact becomes more evident when each component loss is normalized to the total for each response time. Fig. 4 presents the normalized components of energy loss. While turn off loss makes a significant contribution for fast response times, it is a smaller driver for longer response times. Losses generated in the Turn On, On and On-OCD periods remain small contributors to loss, regardless of response time.

A note of caution on the avalanche energy. For response times of less than 4.5 µs, the value from the simulation appears to be below the data sheet limit of 15 mJ for repetitive avalanche rating. However, the limit should be calculated using the transient thermal impedance of the MOSFET, avalanche duration and the avalanche duty cycle in order to ensure safe operation.[3] Second, this simulation used a small value for avalanche energy, 0.5 mJ, at the normal operating peak for the circuit, 75 A. The avalanche energy rose by a factor of 10 during the overcurrent event, with a response time of approximately 2 µs. If this was an application where the MOSFET was normally operated in an avalanche mode with a higher level of energy, it would be quickly driven past the device's repetitive avalanche rating during a repetitive overcurrent event.

Finally, the model is used to develop average power loss as a function of response time for hard or repetitive overcurrent events. Average power is calculated by multiplying the energy loss by the frequency of the pulse-by-pulse current limit. Fig. 5 shows average power loss versus response time for three frequencies.

Two conclusions can be drawn from this figure. First, regardless of frequency, average power loss increases significantly with slower response time. This loss may be higher than normal operating losses, potentially driving operating temperatures past their design points. Minimizing the protection response time minimizes the average power loss in a repetitive overcurrent mode of operation.

A second conclusion is that even relatively moderate frequencies — 5 kHz to 10 kHz — generate losses that will drive the MOSFET junction temperature past absolute maximum ratings, with response times of 2 µs and above. For the case of a 10-kHz frequency, a response time of 2 µs generates nearly 80 W of loss. Assuming a heatsink operating temperature of 80°C and a thermal resistance from junction to heatsink of 1.5°C/W, the junction temperature would approach 200°C. In this case, a secondary level of shutdown such as a pulse count routine would be required to provide adequate protection.[4]

Test Circuit

To demonstrate the effectiveness of fast overcurrent protection and the impact of response time on power dissipation, a test circuit was built. A simplified schematic for this circuit is shown in Fig. 6. In the power section of the circuit, a TD-75 OCD is connected in series with the drain of an IRFZ48V MOSFET. This series combination is connected across an adjustable dc power supply.

The TD-75 is a Hall-effect-based current detector whose output goes low when a 75-A threshold is exceeded. It has a fast response time, and its output is isolated from the sensed current so that it can be placed in the drain section of the circuit without providing further isolation. A 4700-µF aluminum electrolytic capacitor and a 10-µF metalized polyester capacitor are placed across the power supply connection to minimize the circuit impedance. To achieve desired current rise times, the dc voltage is adjusted. For this circuit, an input voltage of 18 V provided an initial current rise rate of 75 A/µs.

The control, protection and gate-drive logic sections of the circuit are composed of an SE555 timer driving the clock input to a 74AC74 D flip flop, which drives a TC427 gate-driver IC. The data input to the flip flop is pulled high so that whenever the IC is clocked, the gate of the MOSFET will be driven to 15 V.

Protection is provided by connecting the output of the TD-75 to the reset input of the flip flop. When the TD-75 detects an overcurrent event, its output resets the flip flop, which forces the TC427 to force the IRFZ48V gate low for the remainder of the clock cycle. In order to adjust the protection response time, an adjustable delay was added to the output of the OCD. A microcontroller is also used in the circuit to provide overall circuit supervision and control.

A photograph of the test circuit is shown in Fig. 7. The heatsink is a 3-in. × 2.5-in. × 0.25-in. piece of aluminum, and it is used to provide electrical connection to the drain of the MOSFET as well as heat dissipation. A 6-in. current loop is included to provide a probe point to display current on the oscilloscope.

Table 3. Test circuit input measurements demonstrating dramatic increase in input power with slower response time, consistent with spreadsheet model.
tD (µs) VIN (V) IIN (A) PIN (W)
1.1 17.81 0.306 5.45
2.0 17.73 0.500 8.87
3.0 17.62 0.778 13.71


Test Results

This circuit was run at a 1-kHz frequency with three different response times. The first was 1.1 µs, which is the response time of the TD-75 used in the circuit. The two remaining runs were made with delays added to provide response times of 2 µs and 3 µs. Table 3 shows power input measurements for the three cases. It shows a dramatic increase in input power when response time is slowed. While not all of this power is dissipated in the MOSFET, it does show general agreement with the results provided by the simulation.

Waveforms for the 3-µs case are shown in Fig. 8. The peak current for the 3-µs case hit a peak of 260 A. This is 77 A higher than the 1.1-µs case, but lower than expected based on the initial current rise rate of 75 A/µs. The rise rate decreases over the pulse duration. This is related to the increasing drop across the MOSFET at higher currents and the sag in the dc power supply during the duration of the current pulse.

Even with this decrease in the rise rate of current, the peak current is coming dangerously close to the absolute maximum peak pulse current rating. A stiffer power source, or a slower response time, would force the pulse current past the absolute maximum rating for the IRFZ48V. For direct comparison of the three response times, Fig. 9 shows the corresponding current waveforms on the same plot. As expected from the simulation, the current waveforms have an identical form prior to overcurrent shutdown. Slower response times impact the later portions of the waveform.

References

  1. “IsoSense Over Current Simulation Spreadsheet,” www.isosense.com.

  2. “Current Rating of Power Semiconductors,” International Rectifier Application Note AN-949, p. 5, www.irf.com/technical-info/appnotes/an-949.pdf.

  3. “Murray, A.; McDonald, T.; Davis, H.; Cao, J.; Spring, K. “Extremely Rugged MOSFET Technology with Ultra-low RDS(ON) Specified for a Broad Range of EAR Conditions,” pp. 4-7, Presented at PCIM 2000, www.irf.com/technical-info/whitepaper/pcim2000.pdf.

  4. Kazmirski, T. “Fast Acting Over Current Power Circuit Protection Scheme,” Presented at Power Systems World 2005, www.isosense.com.


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