While high efficiency is the goal; it may simplify the task to focus on losses instead. Power losses are easily attributed to specific devices, so a design that minimizes losses will naturally maximize efficiency. Also, a focus on losses highlights where the largest efficiency gains might be realized. Reviewing the selection process for the higher loss components will more easily realize efficiency improvements than similar reviews of less lossy components.
Calculating the power loss caused by a device is not the same as calculating the power dissipation within a device. When considering the temperature rise and reliability, it is important to know how much power is actually being dissipated within a given device. However, when selecting a device for efficiency, it is much more important to understand the power loss caused by that device, even if that power is dissipated in other circuit components. For example, when designing a snubber circuit, it is the charging and discharging of the capacitor that causes power loss, but it is the resistor that actually dissipates that power. The same is true in a MOSFET. While gate drive power is typically dissipated within the driver, the power loss must be attributed to the MOSFET, even if it doesn't actually heat up the MOSFET itself. Power dissipation and power loss equations may be different and shouldn't be used interchangeably.
MOSFET LOSS FACTORS
There are a number of different loss factors caused by switching MOSFETs in switch mode power supplies: conduction loss, switch transition loss, body diode conduction loss, gate drive loss, output capacitance loss and reverse recovery loss. For the purpose of MOSFET selection, these can be divided into three groups: conduction losses as a result of the finite resistance of the MOSFET; switching losses as a result of the finite time it takes to turn the MOSFET on and off; and fixed losses that are independent of the finite resistance or finite switching time. Given a MOSFET technology, switching losses are proportional to MOSFET size while conduction losses are inversely proportional to MOSFET size. Selecting an optimal MOSFET is the act of balancing MOSFET size between conduction and switching losses.
The dynamic performance section of a MOSFET datasheet typically shows a number of parasitic charges. On newer datasheets you might find total gate charge (QG), pre-threshold gate-to-source charge (QGS1), post-threshold gate-to-source charge (QGS2), and gate-to-drain charge (QGD), while older datasheets might not list all of these charging factors. While all of these charges are important to determine the exact switching of the MOSFET, only those most tightly linked to the transition of a MOSFET from its high impedance OFF state to its low impedance ON state are critical for MOSFET selection. Figure 1 shows the relationship between gate voltage and gate charge for a typical power MOSFET.
This transition occurs as the gate drive voltage transitions from its threshold voltage (Vt) to the plateau voltage (VPlat). After this, during period four, the MOSFET channel resistance improves only a small amount during and switching losses are virtually zero. The predominant charges that define this period are the post-threshold gate-to-source charge (QGS2) and the gate-to-drain charge (QGD). These two factors summed form the switching charge (Qsw) that best defines the switching time, periods two and three, where the vast majority of switching losses occur. When QGS2 is not given as a separate factor, it can typically be estimated as ½ QGS (QGS1 + QGS2). Figure 2 is a plot of a typical power MOSFET's voltage and current during switching.
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SWITCHING AND CONDUCTION LOSSES
Since switching losses are proportional to MOSFET size and conduction losses have an inverse relationship to MOSFET size, there exists a point where their sum, total loss, is minimized. This drives the MOSFET optimization process, selecting the MOSFET that has minimum total losses. To that end, we will define two parameters. J will be the switching losses per unit switch charge (W/nC) and K will be the conduction losses per unit drain-source on resistance (W/mΩ). Losses that are independent of MOSFET size have little impact on MOSFET optimization, so are not included in J or K equations.
Once the equations for J and K have been derived for a particular MOSFET in a topology, the J/K ratio is compared to the RDS(ON) / Qsw ratio of available MOSFETs. Since J = switching losses /QSW and K = conduction losses / RDS(ON), conduction losses = switching losses when RDS(ON) / Qsw = J/K. Thus, the MOSFET with RDS(ON) / Qsw = J/K will exhibit equal conduction and switching losses, the lowest total losses and thus the best efficiency within that MOSFET family. Even if the exact ratio is not available, this method allows a designer to quickly narrow selection to the nearest two MOSFETs from each of two or three families, allowing the designer to compare a handful of most likely devices from the thousands available, greatly reducing the time and effort associated with MOSFET selection.
APPLYING THE J/K METHOD
There are high-side (Q1) and low-side (Q2) switching MOSFETs in a synchronous BUCK converter (Figure 3), with differing J and K equations. Equations 1-4 define J and K during continuous forward conduction:
QG/Qsw is the total gate charge per unit switch charge. This is constant for a given MOSFET technology and gate drive voltage, but may need to be updated for different MOSFET technologies or changes in gate drive voltage. It can be estimated to be two for 5-V gate drive, three for 8-V gate drive, and four for 10-V gate drive.
fSW is the switching frequency at the target operating point.
IDRIVE is the available drive current while delivering the switch charge. It typically can be estimated by (VGATE - Vth) / (RDRIVE + RGATE)
VDRIVE is the source voltage for the gate drive. In many applications where the gate drive voltage is generated by a linear regulator from the input voltage, this is the input voltage, but it may be another bias voltage.
Vfd is the forward voltage drop of the body diode of the low-side FET.
Since the body diode is carrying the inductor current when both MOSFETs are off, the drain voltage across the low-side FET during switching is only the forward drop of the diode.
Low-side body diode conduction losses are ignored since they are virtually unchanged between MOSFETs with the same forward diode drop, and are primarily defined by the driver's anti-cross conduction dead-time and the forward diode drop.
In this example, we selected a MOSFET for a 12V to 1.8V @ 10A converter switching at 600 kHz using the TPS40192 synchronous BUCK controller. The design is optimized for 60 percent load, or 6A, for good balance between light-load and full load efficiency. J and K are calculated for the high-side MOSFET as follows:
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Looking through TI's NexFET™ devices, we find a likely candidate, the CSD16412Q5A with RDS(ON) = 13mΩ and Qsw = 1.4nC (ratio = 9.29).
J and K are calculated for the low-side MOSFET as follows:
Again reviewing TI's NexFET™ devices, we find the CSD16407Q5 with RDS(ON) = 2.5mΩ and Qsw = 6.15nC (ratio = 0.41).
J/K SELECTION WITH DUAL MOSFETS
Sometimes you may want to either select the same MOSFET for both the high-side MOSFET and low-side MOSFET or to use a dual device with both MOSFETs in a single package. With very different J/K ratios for the high-side and the low-side, how does one select the most efficient MOSFET within this constraint? While averaging the two J/K ratios may seem like a straight-forward solution to this issue, it ignores a bias towards the MOSFET dissipating more power. Instead, the J and K values of both the high-side and low-side MOSFETs should be summed before the ratio is calculated. This weights each MOSFET proportional to its total power loss, thus balancing the total switching losses with the total conduction losses for the most efficient result.
Using the same design above, but limiting the selection to using the same MOSFET for both high-side and low-side, the optimized J/K ratio would be:
In this case, TI's NexFET™ CSD16404Q5A, with an RDS(ON) = 5.6mΩ and QSW = 3.2nC (Ratio = 1.78) would be the best potential choice.
MULTIPLE POINT OPTIMIZATION
Another application of the ratio of sums for the J/K method is optimizing for multiple points. This works best in systems with known load duty cycles where each operating point can be weighted by the operational time at that point. As long as both J and K of each operational point are equally weighted, the process works and selects the MOSFET with the lowest total energy loss at those operational duty cycles.
For example, a radar system will spend 2ms transmitting followed by 10ms receiving reflections. The designer determines the need to deliver 10A of current during a transmit period, but only 4A during a receive period. By selecting a MOSFET with:
Designer selects a MOSFET that offers the lowest total power loss over the entire 12ms cycle, thus optimizing the design for overall efficiency.
PARALLELING MULTIPLE MOSFETS
Sometimes multiple MOSFETs in parallel are required. While placing two identical MOSFETs in parallel does little to change their RDS(ON) x Qsw product, much like paralleling multiple MOSFET cells within a discrete device, it significantly alters the RDS(ON) to Qsw ratio. Each MOSFET in parallel reduces the resistance and increases the gate charge. Paralleled MOSFETs have 1/N2 the RDS(ON)/ Qsw ratio of individual MOSFETs. To apply the J/K method here, choose a MOSFET such that:
Where N = number of MOSFETs in parallel.
MOSFET selection is simplified by focusing on losses caused by the MOSFET. MOSFET selection for maximum efficiency is a balance between increasing MOSFET size to reduce RDSON, and reducing size to reduce switching charge. You can now summarize an application operating point with a simple ratio of switching and conduction losses. The J/K method allows you to quickly and efficiently narrow MOSFET selection from a vast array of available devices to a limited number of suitable MOSFETs by comparing available devices to this simple ratio of switching and conduction losses.