Power Electronics

Discrete Components Enable Bold PoE Solutions

While integrated components for Power over Ethernet (PoE) applications can provide ready solutions for PoE-powered devices, understanding the PoE specifi cation can enable lower-cost discrete solutions.

For the PDF version of this article, click here.

Thanks to IEEE 802.3af, Ethernet data transmission lines may now conduct a specified amount of power. Enabling PoE brings a variety of advantages and is making a profound impact throughout the telecommunications industry. Access points are now unshackled from the electrical cord connected to the nearest available ac outlet and placed in locations that best serve the user's needs.

As the total number of powered devices (PDs) is increasing, the demand for cost-effective designs is growing. Design engineers who understand the specification are creating additional value through optimization of the signature and detection circuitry and dc-dc converter stage.

PoE installation only requires users to run one Ethernet cable to the access point for supplying both power and data. Also, power-sourcing equipment (PSE) detects the presence of a PD (e.g., an access point or Ethernet hub) and injects applicable current into the data cable. An access point can operate solely from the power it receives through the data cable. Remote devices such as voice-over-Internet protocol (VoIP) phones, security cameras, transducers and sensors, and wireless peripherals all now require only the Ethernet cable for data and power. Because of this ease of use and flexibility, PoE offers a variety of benefits.

IEEE 802.3af outlines two power entities for PoE: PSE and PDs. The PSEs typically provide 48 Vdc nominal to the LAN cables while the PDs are small dc-dc converters at the load end of the cables that transform the 48 V to logic levels such as 5 Vdc or 3.3 Vdc, or both, to power the communications equipment. Because only 48 Vdc is used, PoE conforms to Underwriters Laboratories' (ULs) safety extra-low voltage (SELV) classification.

Table. PoE classifications.
0 0.44 W 12.95 W 0 mA 4 mA Open circuit
1 0.44 W 3.84 W 9 mA 12 mA 217 Ω
2 3.84 W 6.49 W 17 mA 20 mA 135 Ω
3 6.49 W 12.95 W 26 mA 30 mA 91 Ω
4 TBD TBD 36 mA 44 mA 62 Ω

Design engineers are optimizing the signature and detection circuitry by selecting discrete solutions versus fully integrated ICs. The requirements for signature and detection can easily be met by a few discrete components, and once the circuit is understood, it can be reused in each design. The discrete approach is also more cost-effective than integrated ICs that perform the same function.

One interesting aspect of discrete PoE solutions is the use of other types of application-specific ICs (ASICs) to implement PoE functions. For example, the use of a hot-swap controller IC can be used to perform inrush-current limiting for a PD, as will be shown in this article. Alternative IC applications such as this enable cost reduction and supplier diversification. They also challenge designers with the possibility of incorporating proven production components into their PD designs.

It is important for designers to optimize the dc-dc converter stage when designing each PD. The PoE specification creates five levels of classification based on the output power requirement (table). The default power level is set to less than 15 W per PD. While 15 W is the maximum power allowed, most devices require less than half that power. For example, most VoIP phones are less than 6 W and print servers are less than 2 W. Therefore, it is possible to power two VoIP phones from one Ethernet cable, because some systems allow the ability to “daisy chain” several devices on a single 15-W cable. The dc-dc converter stage in each PD can be optimized for the expected power level versus having the full power rating available to a PD. This can result in a significant cost savings in every PD device that is 6 W or less.

PD Requirements

PDs should be able to operate with a maximum average input power of 12.95 W, and tolerate an input voltage range of 36 Vdc to 57 Vdc. In addition, a certain protocol is required in which the PD is detected (signature mode) and then classified (classification mode) according to its maximum power level.

During signature mode, the upstream PSE equipment detects the PD by injecting two different voltages between 2.8 Vdc and 10 Vdc into the PD input terminals. If the detected impedance of the PD as measured by the V/I slope is above 23.7 kΩ and below 26.25 kΩ, the PD is considered present. If the impedance is less than 15 kΩ or greater than 33 kΩ, the PD is considered not present and no further voltage is applied.

During classification mode, the PSE classifies the PD according to its intended power level. The PSE again sources a voltage between 14.5 Vdc and 20.5 Vdc to the PD. The classification is determined by the current drawn by the PD upon application of this voltage, and is summarized in the table.

In addition to the signature and classification circuitry, the PD must also include circuitry to limit the inrush current from the PSE to 400 mA when the input voltage is applied. This also prevents any quiescent currents or impedances caused by the dc-dc converter during the signature and classification processes.

DC-DC Converter Solution

Fig. 1 shows an example of a PoE, dc-dc converter with all of the associated signature, classification and inrush-current-limit features required. It is a 6.5-W dc-dc converter optimized for Class 1 and Class 2 PDs. The design is implemented around ON Semiconductor's NCP1031 monolithic PWM controller and high-voltage MOSFET. The circuit is a discontinuous mode (DCM) flyback converter with the conventional TL431 and optocoupler voltage feedback scheme. The input uses a differential-mode pi filter comprised of C3, L1 and C4. Control chip startup is accomplished when the undervoltage (UV) terminal at pin 6 exceeds 2.5 V. The resistor-divider network of R7, R8 and R9 sets the chip's UV and overvoltage (OV) levels to 35 V and 80 V, respectively. Internal startup bias is provided through pin 8, which drives a constant current source that charges VCC capacitor C7. Once U2 has started, the auxiliary winding on transformer T1 (pins 2 and 3) provides the operating bias voltage via diode D4 and resistor R11.

Voltage spikes caused by the leakage inductance of T1 are clamped by the network of C5, D6 and R10. The actual power rating on R10 will be a function of the primary to secondary leakage inductance of T1, which is ideally minimal. Capacitor C6 sets the switching frequency of the converter to approximately 220 kHz.

Because of the required secondary isolation, a TL431 (U4) is implemented as an error amplifier along with optocoupler U3 to create the voltage-sensing and feedback circuitry. The internal error amplifier in U2 has been disabled by grounding pin 3, the voltage-sense pin, and the amplifier's output compensation node on pin 4 is used to control the pulse width via the optocoupler's photo transistor. The output voltage sense is divided down to the 2.5-V reference level of the TL431 by R16 and R17, and closed-loop bandwidth and phase margins are set by C9 and R15. C8 on the primary side provides noise decoupling and additional high-frequency roll-off for U2. This implementation provides output regulation better than 0.5% for both line and load changes, and a closed-loop phase margin of better than 50 degrees.

Output rectifier D5 is a 3-A Schottky device for enhanced efficiency, and the output voltage is filtered by the pi network comprised of C11, L2 and C12. Typical VPK-PK noise and ripple on the output are below 100 mV under all normal load and line conditions. C13 provides for additional high-frequency noise attenuation. Typical input to output efficiency is in the area of 75% at full load. Higher efficiencies can be achieved by replacing D5 with a MOSFET-based synchronous-rectifier circuit (see ON Semiconductor application note AND8127 for implementing a simple synchronous-rectifier circuit to a flyback topology).

Overcurrent protection is provided by the internal peak-current-limit circuit in the NCP1031 (U2). The circuit can provide a continuous output current of 1.3 A at 25°C and surge current up to 1.5 A, before overcurrent or overtemperature limiting ensues.

Signature and Classification Details

Referring to the schematic in Fig. 2, the input signature and classification circuitry is designed around a few discrete and inexpensive components that include the TL431 programmable reference, a 2N7002 signal-level MOSFET, a 2N5550 NPN transistor, an NTD12N10 MOSFET, several Zener diodes and a few resistors and capacitors. For signature detection, a 24.9-kΩ resistor (R1) is placed directly across the input.

Note that during signature detection, the input voltage is below 10 V and the constant-current source formed by U1, Q2 and R4 is off because of the 9.1-V Zener that must be overcome to bias this circuit. Note also that MOSFET Q3, which functions as a series input switch in the return leg of the dc-dc converter, will be off until the input voltage exceeds approximately 27 V. This voltage is the sum of D2's Zener voltage and the gate threshold of Q3.

As the voltage is ramped up to the classification level, D1 conducts above approximately 9.8 V and the current source formed by U1, Q2 and resistor R4 turns on, and the current is precisely limited by the reference voltage of U1 (2.5 V) and the classification resistor R4. Once classification is verified, the input can now ramp up to the nominal 48 V. Once this voltage exceeds the sum of Q3's gate threshold and D2's Zener voltage, Q3 will start to turn on. It will not turn on abruptly, but will operate in its linear region momentarily due to the RC time constant created by R6 and C2.

The momentary operation in the linear region allows for inrush-current limiting because Q3 will act like a resistor during this period. D3 clamps the voltage on Q3's gate to 15 V, while R5 provides a discharge path for C2 when the input from the PSE is off. MOSFET Q1 also will turn on at the same voltage level as Q3, and this will switch off the current source formed by U1 and Q2 so as to reduce additional current drain from the input.

Future Opportunity

The industry is currently defining the specifications for extending the power capability of PoE. The new PoE Plus 802.3at specification will enable PDs greater than 15 W. This will open up new applications such as battery charging for laptops and enhanced features of existing products such as VoIP phones.

Until the specification is finalized and released, design engineers will be evaluating several solutions. As with the existing PoE classification and detection circuits, a discrete approach will allow the flexibility to implement a cost-effective solution quickly.

The circuit of Fig. 2 shows a 25-W PoE Plus dual-output dc-dc converter (3.3 V and 5 V) that will provide up to 3 A on either channel. The converter circuit uses the ON Semi NCP1216 current-mode controller (U2) driving an MTP20N15 MOSFET (Q1) in a DCM flyback configuration. This assumes a Class 0 circuit (POUT > 13 W), and no classification circuitry is necessary because the input source current required by the PSE during the classification process is essentially zero. Resistor R1 still provides the required signature current. The final classification and detection requirements of 802.3at are still being defined, so this may change.

U1 is ON Semi's NIS5111 hot-swap controller. It is conveniently used in this application as a low-RDS(ON) MOSFET input switch for improved efficiency and control. After classification is verified, the NIS5111 senses the input voltage across pin 4 to pins 5, 6 and 7. Once the user-selected undervoltage lockout (UVLO) threshold of 38 V has been reached, the gate of the internal SenseFET will begin to charge slowly. After a delay of several milliseconds, the current through the SenseFET is increased at a controlled rate until the current limit is reached.

The SenseFET will then enter a constant-current mode of operation until capacitor C4 is completely charged. Turn-on delay can be extended with capacitor C3 and the current limit selected by resistor R4. If the bus voltage rises above the OV threshold, the flow of current will be inhibited by the adjustable overvoltage lockout (OVLO) feature.

Capacitor C2 is optional to prevent OV tripping. In the event of a fault condition such as a short circuit or overload, the NIS5111 will limit the current until a die temperature of 135LC is reached. The built-in thermal protection will then shut down the SenseFET until the temperature reaches 95°C, at which time it will enter into auto-retry mode.

Future Discrete Solutions

The advantages of PoE justify the efforts to implement the required PoE power circuitry into PDs. Most devices require only half of the total available power, and significant cost savings in each PD can be achieved by sizing the solution to the classified power requirement. An optimized solution in both the classification/detection circuit and the dc-dc converter section will lower the cost of each PD and result in a significant total-system cost savings.

Once designers understand the theory of implementing the signature, classification and inrush-current limiting for PDs, they can create value for their PoE products. This will allow them to have a product advantage in size, efficiency or cost over other fully integrated solutions, which are more expensive and typically not as flexible. It will become even more important to understand the technical requirements of PoE as the new PoE Plus 802.3at specification is released and designers are challenged to quickly release new products.


  1. IEEE Standard 802.3af (Ethernet power transmission standards).

  2. On Semiconductor Application Note AND8247, “Application Note for a 6.5 W POE DC to DC Converter.”

  3. On Semiconductor Application Note AND8119, “Design of an Isolated 2.0 W Bias Supply for Telecom Systems Using the NCP1030.”

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.