The trend toward more dense and efficient quasi-resonant converters has led to the development of high-efficiency converters capable of higher switching frequencies. For this reason, Fairchild's QR PWM converters have drawn much attention because of their high efficiency, high switching frequency, and high power-density capabilities.
These low-cost, high-efficiency devices combine a boost converter PFC stage and a single flyback PWM stage. Both stages are properly controlled by the single combo controller (Fig. 1).
OPERATION PRINCIPLE OF PFC STAGE
The turn-on sequence of the PFC MOSFET is determined by the zero current detection, since the PFC stage operates in boundary conduction mode. The mechanism can be achieved by detecting the information on an auxiliary winding of the PFC inductor (Fig. 1). Once the detected voltage signal is lower than the triggering voltage, the PFC gate will be turned on to initiate a new switching cycle. View Article equations
As for the turn-off sequence, the traditional method is with fixed on-time control. In steady state, with one switching cycle, input voltage, Vg, can be viewed as constant. As shown in Fig. 2, when MOSFET Q b is switching, inductor current ramps up and down linearly, and peak value can be expressed as:
The feedback signal of the PFC output voltage in steady state is almost constant during one-half ac cycle, so the fixed-frequency sawtooth generator achieves fixed on-time control. Therefore, iL,peak will automatically follow input voltage, Vg, as a natural PFC mechanism. Fig. 3 shows the typical inductor waveform in one-half ac cycle. Using the average area of the inductor current's triangular waveform, average current, i L,avg, can be derived from Eq. 1 and expressed as:
The problem with fixed on-time control is the error amplifier's narrow bandwidth results in poor transient response. To improve this, a multi-vector error amplifier was built in a trans-conductance-type controller. The PFC output voltage is detected by an external voltage divider consisting of R1 and R2 (Fig. 4). When PFC output-variation voltage reaches more than 6% or less than 8% of the reference voltage, V ref, the amplifier adjusts its output sink or source current to increase loop response and simplify the compensated circuit.
The output of the error amplifier is compared with the internally generated sawtooth waveform to determine the on time of the PFC gate (Fig. 5). Normally, with a lower feedback-loop bandwidth, the variation of the PFC gate on time should be very small and almost constant within one input ac cycle. However, a PFC circuit operating at light load has a usual defect — zero crossing distortion — which distorts input current and makes the system's THD worse.
A built-in THD optimizer improves THD at light load, especially with a high input voltage. The optimizer samples the voltage across the current-sense resistor, and the sampled voltage is added to the sawtooth waveform (Fig. 5) to modulate the on time of the next switching cycle. As a result, the compensated PFC's on time around the valley of ac input voltage will be wider than the original, while PFC on time around peak voltage will be narrower. Fig. 6 shows timing sequences of the PFC MOS and the shape of the inductor current. Fig. 7 shows the difference between the fixed on-time mechanism with and without the THD optimizer during a half ac cycle.
PROTECTION FUNCTIONS OF THE PFC STAGE
With ac voltage detection, the controller can perform ac undervoltage protection. Ac input voltage is detected with a resistor divider and an RC filter, (Fig. 1), such that the filtered signal is proportional to the ac voltage level. When ac voltage drops after a period of de-bounce time, undervoltage protection is activated and the output of the error amplifier, Vcomp, will be clamped at a low level.
Because the duty of PFC switching is determined by comparing the sawtooth waveform and Vcomp, (Fig. 5), lower Vcomp results in smaller PFC on-time; therefore, the energy converged will be limited and PFC output voltage will be decreased. When the feedback PFC output voltage, Vinv, is lower than the threshold voltage, the controller will immediately stop all PFC and PWM switching until VDD (the power supply IC) drops to turn-off voltage and then raises to turn-on voltage again. Once ac input voltage is back to normal and VDD reaches turn-on voltage, switching operations will return to normal.
OPERATION PRINCIPLE OF PWM STAGE
The PWM turn-on sequence is determined by valley detection. During the PWM switch's off time, when transformer/inductor current discharges to zero, the transformer/inductor and the parasitic capacitor of the PWM switch resonate. When the drain voltage of PWM switch falls, the voltage across an auxiliary winding, Vaux will also decrease proportionately since the auxiliary winding is coupled from the primary winding.
Once Vaux resonates and falls to negative, the controller (Fig. 8) will internally clamp V DET at a low level, Vclamp, and flow out a current, iDET. The magnitude of iDET is proportionate to the amplitude of Vaux. The valley detector will compare iDET with a threshold level, and if iDET rises over this level, PWM gate will be triggered.
The PWM turn-off sequence is determined by the output feedback voltage, VFB, and the PWM MOSFET sensing current. Feedback voltage is proportionate to the output loading. Once the sensed current signal reaches VFB, the PWM MOSFET will be turned off.
As mentioned, PWM will initiate a new switching cycle once the first valley signal is detected. However, when the output load is decreased, the transformer's energy is also decreased, and so is the magnetizing inductor's discharge time, leading to extremely high switching frequency at light load.
The off-time modulation technique is used to solve this problem by regulating switching frequency according to VFB. When output load is decreased, VFB becomes lower, and extends the PWM minimum off time, tOFF-MIN, internally (Fig. 9). Minimum off time can be viewed as a period of time that blanks the valley signal. After t OFF-MIN, once the valley signal on the auxiliary winding is detected, the PWM gate signal will be sent out to initiate a new switching cycle.
With the frequency-regulation curve, at light load, the power system can perform extended valley switching and reduce switching loss. According to Fig. 9, when VFB is lower than VG, tOFF-MIN is extended to tb, so that the PWM stage enters burst-mode operation to further reduce switching frequency and improve conversion efficiency.
Generally, when the power switch turns off, there is a delay from the gate signal's falling edge to power-switch off. This is produced by the controller's internal propagation delay, turn-off delay time due to the gate resistor, and the PWM switch gate-to-source capacitor, Ciss,.
Under various ac input voltages, this delay time varies maximum output power at the same PWM current-limit level. Higher input voltage leads to a higher maximum output power limit since the rising slope of the magnetizing inductor current is higher. To make the maximum output-power limit the same level under different input voltages, the controller must regulate the maximum limit voltage of the PWM current sense, VCS-limit, to limit the PWM switching current.
In Fig. 1, when PWM MOSFET Qf is on, the auxiliary winding voltage, Vaux, carries the information of input voltage, Vin, expressed as:
where Na and Np represent the number of turns of auxiliary and primary windings, respectively. So, as Vin increases, so does the magnitude of Vaux. As mentioned, the controller flows out a current, iDET, when Vaux is negative, and iDET can be expressed as:
where RDET is the resistor connected between the auxiliary winding and the controller (Fig. 8).
Since the current, idet, is in accordance with Vaux, which carries input voltage information, the controller can depend on idet to regulate VCS-limit and overpower compensation at different line voltages. Fig. 10 shows the characteristic curve of i det vs. vCS-limit. As input voltage increases, Vaux and idet increase, and the controller regulates VCS-limit to provide compensation.
Besides valley detection and overpower compensation, VDET also carries output voltage information when Qf is off, so output overvoltage protection can be achieved. During the discharge time of the PWM transformer/inductor, the voltage across the auxiliary winding is reflected from the secondary winding (Fig. 11). The flat voltage of V DET is proportional to the output voltage and can be expressed as:
where Ns is the number of turns of the secondary winding, and RDET and RA are the resistors connected between auxiliary windings to the controller (Fig. 8). The controller can sample this voltage level to perform output overvoltage protection. The sampled voltage level is internally compared with a threshold voltage; once VDET exceeds this, protection is activated and the IC enters latch mode. The controller rapidly protects this cycle-by-cycle sampling in case of output overvoltage. Protection voltage levels can be determined by the external resistor dividers, RA and RDET.