Power Electronics
TrenchFETs Enhance DC-DC Converter Performance

TrenchFETs Enhance DC-DC Converter Performance

Generation 3 TrenchFETs enhance dc-dc converter performance/size.

High-density dc-dc converter manufacturers want improved efficiency, smaller footprints, and lower cost — despite increasing output loads. With this, power MOSFET suppliers must produce better-performing devices, which is no small task. Driving factors for this are

  • Higher efficiency with reduced switching losses,
  • Low RDS(on),
  • Lower power dissipation,
  • Improved reliability,
  • Improved UIS,
  • Eliminate need for parallel devices for higher power,
  • Lower gate charge and capacitance,
  • Faster switching speeds,
  • Increased power package density, and
  • Reduced costs.

Boosting Cell Density

Trench-gated vertical DMOS silicon is common in today's industry, providing documented and established advantages over its planar counterparts. This innovation is ongoing with TrenchFET Generation 1 as the baseline for the industry's Trench technology. Generation 2 has a shallow source, lower Vth, and a thinner substrate that improves RDS(on).

Typical Generation 2 densities for N-channel and P-channel trench devices alike range between 32M to 50M cells per square inch. Depending on specific manufacturing processes, on-resistances of the industry's better SO-8 30V n-channel devices (the dc-dc benchmark) are in the 4mΩ to 5mΩ region with gate charge levels (Qg) of <25nC in the Si4842DY.

To increase cell density, device engineers must focus on lateral scaling of the cells. With this, the density per wafer increases dramatically, thereby lowering the overall on-resistance. However, for high switching dc-dc applications, the ultra-low RDS(on) is only half the focus, as power dissipation (Pd) includes conduction, gate, and switching losses.

For optimum MOSFET silicon performance, implementation of lateral and vertical scaling are necessary. We were able to lateral scale cell density to more than 170M cells per square inch, and to vertical scale the trench to minimize the gate capacitance and keep total gate charge (Qg) to levels previously seen only in lower cell density devices (sub 40nC). Fig. 1 shows the difference between existing 32M cell density and the effects of improving — laterally and vertically — the cell structure on the latest higher-density generation silicon.

From the two cell cross-sections in Fig. 1, you can see that MOSFET lateral scaling results in fine patterning, scaling of channel width, smaller die area, and consequently lower RDS(on). The vertical scaling improvement gives a low thermal budget, thin epi-layer, short channel, and shallow trench, resulting in Qg minimization.

Our Generation 3 silicon technology development combines vertical and lateral scaling methods to shorten the channel, lowering the RDS(on), and it implements a shallow junction and trench process that reduces Cgs and Cgd for low RDS(on)×Qg for higher-frequency PWM optimization.

Fig. 2 shows the effect of shallower trench depth on FET gate turn-on characteristics. The Miller capacitance and consequent plateau on the Vgs turn-on is effectively reduced, hence the device will be fully saturated faster than longer-trench-depth silicon.

On paper, it is clear to designers that TrenchFET silicon advances offer significant characteristic improvements, static and dynamic, over today's devices. However, no device, even new-generation silicon, can offer the best parameters in all performance areas. This is where the manufacturer optimizes according to the design, and the designer optimize according to the circuit.

MOSFET Optimization

It's no longer acceptable to compromise dc-dc converter efficiency by selecting an established, standard device. Take the 30V N-channel Si4420DY SO-8 MOSFET, for example. As the Generation 1 device of choice for dc-dc synchronous buck or secondary rectification converters just two years ago, it was an industry leader. The Si4420DY has a maximum on-resistance value of 9mΩ at a Vgs of 10V and typical gate charge of 35nC, which still can be classed as a low figure of merit (FOM) of 315.

A comparison of the Generation 1 Si4420DY with the Generation 2 Si4880DY demonstrates an improvement laterally, with lower RDS(on), and a reduction in total gate charge (Qg) to 19.5nC, yielding an overall FOM of 158. The Si4880DY has a maximum on-resistance of 8mΩ at a Vgs of 10V and typical gate charge value of 19.5nC. Effectively, this is a 50% reduction from the Si4420DY. Lower RDS(on) means lower conduction losses and lower Qg, resulting in lower switching losses. Fig. 3 compares the Si4420DY against the Si4880DY in an “apples-to-apples” efficiency evaluation.

Both devices were used as a high-side and low-side switch, driven by the same synchronous buck controller at 300kHz. A 1% increase in controller efficiency was gained by simply substituting the Si4880DY for the Si4420DY.

Now, with the ability of vertical and lateral scaling in the latest silicon technology process, the best balance of RDS(on) and Qg is possible according to respective circuit requirements. Reducing Cgs and Cgd brings the Qg to record-low levels, and shorter channels offer SO-8 N-channel 30V MOSFETs with RDS(on) values below 4.5mΩ. The Si4364DY, for example, has a maximum RDS(on) at 10V of 4.25mΩ.

High-Side vs. Low-Side

A synchronous rectification converter secondary contains two MOSFET switches, the high side (or inline switch) and the low side (or flywheel switch). Due to the circuit operation, it is known that each switch, high-side or low-side, requires differing criteria to achieve optimum converter efficiency. Traditionally, the standard design approach was to use the same low-RDS(on) and low-Qg device in high- and low-side slots. This is adequate, and with low FOM devices, achieves reasonable efficiencies.

However, we can further optimize respective device selection with an array of latest-generation devices. So, when the cost-per-amp or size-per-amp of generic dc-to-dc converters must be reduced, then switching frequencies must increase, passive component size must be reduced, and efficiency has to increase — which means that even a 1% increase is significant.

High-side switch selection is the simpler choice, as it will be affected by switching and conduction loss. Thus, the lowest FOM is desirable.

When examined in detail, to reduce the overall switching loss the ideal high-side switch must have:

  • Small Rg and Ls to cut the time constants [Tc = Rg(Cgs + Cgd1)]
  • Small Ciss for short current transients
  • Small Cgd for short voltage transients
  • Small Qg (and hence Ciss and Cgd) to reduce the gate charge losses
  • Low RDS(on) to reduce the conduction losses

In the Generation 3 process, it requires shallow trench and short channel length for optimum FOM.

Looking at the low side, there are far more direct and indirect operational parameters and requirements. Table 1 summarizes the requirements.

The low side device requires:

  • Ultra-low RDS(on) to reduce conduction losses
  • Small Qg (hence Ciss and Cgd) to reduce the gate charge loss
  • Qgd-to-Qgs ratio of <1.0 to enable the device to be shoot-through-rugged

For synchronous rectification, the switching losses of the low-side device are not applicable, as the parallel body drain diode or externally connected Schottky diode is in conduction just prior to current transferring to the FET. As a result, no voltage Vds to decay is across the MOSFET.

Relative to the Generation 3 process, the low-side device requires high density and short channel length for lowest resistance and small Qgd to avoid shoot-through conditions. The further benefit of complete silicon manipulation for third-generation technology is the ability to make dc-dc switching devices (low-side) shoot-through-rugged. The Qgd / Qgs is <1.0 and thus there are no issues at switching both devices at speeds in excess of 300kHz.

Traditionally with non-PWM-optimized devices, increasing the switching speed naturally gave rise to greater dv/dt and di/dt switching overshoots. A common problem was that the higher switching transition of the high-side device caused spurious charging of the Cgd of the low-side switch and hence a consequent transient voltage on the low-side gate and, finally, turn-on and shoot-through from dc rail to ground. Therefore, the aim of raising the switching frequency to reduce the size of circuit passive components was counterproductive unless the selection of device (especially the low side) could be manipulated to resist any occurrence of spurious turn-on. Approximate calculation and practice show the order of Qgs to equal two times the Qgd for shoot-through-rugged devices.

Fig. 4 shows a comparison of differing high- and low-side device optimization. Each test used the same synchronous buck converter, load, and circuit with the devices (two in parallel for the high-side and three in parallel for the low-side) switching at a constant 300kHz and 20V input with a 1.5V output.

From the four device selections shown, it's possible to compare the traditional approach of using the same 30V N-channel SO-8 FET as high- and low-side. The least-efficient result used device A, selected as the best-from-family for low RDS(on) and low Qg (FOM = 216). The data in green lines, and under light loading, gives only 86.8% efficiency at best.

The blue data line uses the Si4860DY, a Generation 2 device with 8mΩ and 13nC (FOM = 104) as high- and low-side switch. The result gives an 88% efficiency at light loads, yet falls under increased current.

The orange data line uses devices on the high-side (both low RDS(on) and low Qg) and devices on the low-side with best-in-family RDS(on) and consequently higher Qg (FOM = 174). The efficiency is reasonable under light loads (87.5% maximum) but remains high as the load increases.

Finally, the red line uses Si4860DY devices in the high-side (low RDS(on) and low Qg) and Si4362DY in the low-side. The Si4362DY is the first of the Generation 3 technology N-channel products at 113M cells/in.2. This device is optimized for ultra-low on-resistance and normal levels of Qg (4.5mΩ and 42nC, FOM = 189). The effect of selecting such as a high- and low-side optimized pair is to achieve a maximum efficiency of 88.8% under light load, while still remaining >1% better than the nearest rival combination as the load increases.

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