Power Electronics

Thermal Design and Packaging for Proper Power Management

Packaging and thermal design are driven by increased power density and the many trade-offs in power topology selection.

The world of modular dc-dc converters or “bricks” has evolved at a rapid pace since the first full-brick was commercialized in the mid-1980s. In recent discussions at the Applied Power Electronics Conference (APEC), the sixteenth-brick format was proposed: 1.2 sq in. of PCB area with a staggering 33W to 50W throughput. As brick form-factor diminishes, those using the bricks are pushing for standardized interfaces for trimming output voltage and sequencing to prevent latch-up in load circuitry and preclude undervoltages when enabled into pre-biased rails.

Rack-mounted equipment for the information infrastructure uses a distributed power architecture in which the raw ac power is converted with a high power factor to a distributed dc bus, nominally 48V. Telecom applications use a battery for back up and a -48V bus, primarily to reduce corrosion. The telecom bus operates over a wider range — 36V to 72V — than its datacom counterpart, which has a tighter tolerance. A bus converter converts this bus with isolation at each card (the first use of the brick format). The on-card power is then applied directly to the load circuits. However, in recent years, the proliferation of DSP and digital ASICs has spawned an intermediate bus architecture in which the bus converter delivers an isolated 12V to 14V, which is further converted by point-of-load regulators physically located at the loads on the card.

Switch and rectifier selection takes center stage when the power supply designer selects the topology to match the application, and considers the number of power conversion stages[1] and whether the converter is hard or soft switched. Most bricks employ power MOSFETs for the power switches and low-voltage synchronous rectifiers. MOSFET technology has evolved considerably, presenting designers with trench devices with benchmark RDS (ON) and planar devices with low inter-electrode capacitance. Once the voltage and current rating has been established, device selection depends on which characteristic, switching speed, or RDS (ON) dominates the loss. In recent times, the ratio of CDG to CGS has influenced designers as an indicator of likelihood of shoot-through in high-power, high-frequency, half-bridge power stages.

A perennial trade-off is that of switching frequency with efficiency and electromagnetic interference. Switching losses in the power switches, rectifiers, and control circuitry increase with switching frequency. In modular dc-dc converters, increasing frequency is desirable because it reduces the size of filter and energy storage components. However, in hard switched applications, the increased high-frequency harmonic content in the power devices results in larger displacement currents in the stray capacitances between devices and heatsinks or power planes, and through the interwinding capacitance of transformers. Such displacement currents manifest themselves as common-mode interference.

In dc-dc converter control and drive applications, IC design and packaging has embraced the challenge presented by the brick environment. At the circuit design level, increased integration, inboard high-voltage regulators, higher clock frequencies, and low shoot-through drivers with programmable slew rate are available for new designs[2]. Thermal regulation is a key issue in power IC design. Power ICs have integrated drivers, regulator pass transistors, and power switches arranged at the periphery of the die next to the bond pads. As these devices operate, heat conducts through the body of the die, creating a thermal “map” with isotherms (contour lines of constant temperature). Certain subcircuits — particularly differential circuits where matching is critical — are adversely affected if the individual transistors are positioned on different isotherms. IC layouts must be adjusted so that transistors in such applications see the same temperature at the same time when the device is operating — not a trivial task. Photomicrographs of power ICs often reveal devices that are cross-coupled for first-order cancellation of thermal effects.

The Leadless Leadframe Package (LLP), shown in Fig. 1 on page 24, is a leadframe-based chip scale package (CSP) that enhances chip speed, reduces thermal impedance, and reduces the printed circuit board area required for mounting. The small size and very low profile make this package ideal for the high component density multilayer PCBs used in modular dc-dc converters. The advantages of LLP include:

  • Low thermal resistance,
  • Reduced electrical parasitics,
  • Improved board space efficiency,
  • Reduced package height,
  • Reduced package mass.

IC package design is a painstaking process involving extensive thermal and mechanical modeling with fabrication and measurement stages in which finite element models (see Fig. 2) are compared with spot measurements on the die or by thermal imaging. Generally, spot measurements on the die are accomplished by measuring the forward drop of a diode in a test die incorporated within the new package. This technique is used in many of the remote diode temperature sensing devices[3] that protect the latest generation of microprocessors, DSPs, and digital ASICs. One or more diodes in the test die may also be used to inject heat to verify the thermal characteristics of the die.

Thermal properties of electronic packages[4] are characterized by θJA and θJC. θJA can be defined as an overall package thermal resistance, which is the sum of package internal and external thermal resistance. It can be expressed as:

θJA = θJC + θCA = (TJ - TA)/P

Where:

θJC: (TJ - TC)/P, junction-to-case conductive thermal resistance (°C/W)

θCA: (TC - TA)/P, case-to-ambient convective thermal resistance (°C/W)

P: I (Current) × V (voltage), Device heat dissipation (W)

TJ: Average device junction temperature (°C)

TA: Average ambient temperature (°C)

TC: Case temperature at a prescribed package surface (°C)

θJC is dominated by the conductive thermal resistance within layers of packaging materials, and is highly dependent on the package configuration. If the heat flow is assumed to be perpendicular to each layer of the packaging material, θJC may be expressed as:

Σ ti/(ki Ai)

Where ti, ki, and Ai are the thickness, thermal conductivity, and heat transfer surface area of each packaging material layer (e.g., die attach material, lead frame, die coating, and encapsulant or mold compound).

θCA is the external convective thermal resistance. It's greatly affected by adjacent ambient conditions, package boundary conditions, and conjugate heat transfer.

In the LLP package, low junction to ambient thermal resistance is primarily affected by reducing the resistance from the thermal plane on the PCB to the junction. The cross-section in Fig. 3 shows that the die is soldered to the die attach pad, which is directly soldered to the power plane on the PCB. The area of the PCB power plane dominates θCA in brick applications, where conduction is the primary method of heat transfer and convection cooling is restricted due to the diminishing pitch between cards.

θCA may be improved by using thermal vias in the power plane under the device. This improvement is second order compared with that achieved by increasing the area of the plane to which the LLP is soldered. A comparison between the LLP and a conventional small outline package with the same pin count and die reveals the benefits. Let's take an MSOP-8, where the PCB area is 15 mm2 compared to LLP-8, which takes up 9 mm2. The dramatic difference is in thermal resistance where the LLP-8 exhibits a thermal resistance (θJC) of 40°C/W versus 200°C/W for the MSOP-8.

Where silicon efficiency — maximizing the value added to the device by each processing step — is paramount, multichip and stacked die processing are emerging. In many power ICs, the power devices that occupy a significant area of the device are made in six to 10 mask processing steps, while the rest of the IC in a power IC process is completed in 14 to 26. Co-packaging devices in multichip assemblies allows IC designers to mix technologies for maximum current density and efficiency, where vertical power devices may be included with dense mixed signal IC technology.

A Glimpse Into Package Design

A modular dc-dc converter is a most demanding environment for power ICs. The inexorable push to higher power density and the necessity for higher efficiency drives power IC and package designers to set new standards in thermal resistance and volumetric efficiency. Giving power supply designers a brief glimpse into the package design, measurement, and verification process is an important part of launching a new standard, particularly in power applications where new discrete power packages are a frequent part of the landscape.

References:

  1. Ashley, D. “Cascaded Converters Emerging in Distributed Power Systems.” PCIM Europe March 2003.

  2. Ashley, D., Bell, R. and Lam, E. “Revolutionary Advances in Distributed Power Systems.” Applied Power Electronics Conference Feb. 9-13, 2003.

  3. http://www.national.com/appinfo/tempsensors.

  4. “Package Thermal Characterization,” National Semiconductor Corp. MS011816 August 1999

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