Power Electronics

Technologies Tip the Scales Below 90 nm

Nanometer technologies are the main tool to effectively achieve a real “system on a chip.” Systems, by definition, also include high-voltage interfaces and power components. But is it really possible to integrate all of these power components in ICs with design rules below 90 nm?

The first challenge is the correct partitioning of the whole system. Mostly, because of topology constraints, it is neither possible nor desirable to integrate all the elements of a complete system into a single chip.

Having some experience in the field of integrated circuits for hard disk drives, I know that some functions like read/write circuits must be positioned close to where the action takes place. The drivers for the spindle motor and the voice coil must be far away from the “core” silicon device.

Consequently, in the usual system partition, all the power elements are physically separated from the computational engine. The “brain” of the system may use the most up-to-date nanometer technologies, and the “muscles” may employ the most appropriate BCD or smart power technologies, often based on less aggressive lithography.

However, even in this case, there are problems to be solved. CMOS tranistors with features in the 90-nm region are never completely turned off, giving rise to power consumption problems. Even when they are in the off state (VGS = 0), their “sub-threshold” current steals energy from the battery. So it is not enough to separate the computational engine from the power elements. The nanometer VLSI chip must embed some regulators and switches that fully disconnect it from the power supply. This is the only way to achieve an acceptable power consumption and minimize crosstalk on the signal lines.

But the real question is whether it is possible to design power ICs using the most up-to-date nanometer technologies. The main issue is that the typical gate oxide of these technologies — typically in the range of 35 A — cannot withstand more than 1.8 V. Therefore, for reliability reasons, the gate-source voltage (the driving voltage) of the basic transistor cell is limited. At the same time, overdrive must be enough to minimize RON.

Nevertheless, even dense CMOS technologies can withstand high output voltages. Clever chip designers may use cascode schemes for driving the circuit, and in most cases, achieve acceptable performances up to 5 V. But the real answer for power is to use DMOS structures. DMOS elements can be used to reach a significant drain-source voltage: 100 V is achievable with appropriate drain engineering, even with a gate-source voltage limited to 1.8 V.

A real challenge is to realize in a single IC all the electronics for a microdrive where the power is limited and the space is very small. Here, the big issue is how to mix power elements and VLSI computational blocks on the same device while eliminating unwanted parasitic components. One answer is the well-known silicon on insulator (SOI) technique, which eliminates parasitics at low frequencies.

As smart power designers are well aware, the nightmare of parasitic components in power switch mode can be solved using SOI. Also, if the substrate is well grounded, SOI may be used to create a sort of Faraday cage, embedded in the chip, which isolates high-frequency analog components from the rest of the system.

In the past, SOI suffered from two problems that prevented its use. It was expensive and it increased the thermal resistance of the chip. STMicroelectronics has developed an unconventional approach that solved both problems. As a result, SOI can now be used to integrate ultradense logic and power components on the same chip and at a reasonable cost. And SOI ensures that logic and power elements do not interfere with each other.

Bruno Murari joined SGS (now STMicroelectronics) in 1961, working first in the application laboratory and then in the linear IC design group. In 1972, he became head of linear IC design and development at the company's Castelletto laboratories on the outskirts of Milan, and in 1981, became plant manager for the Castelletto facility. Murari has filed more than 80 patents on smart power technologies, circuits, packages and MEMS components. He has personally designed 10 integrated circuits and has supervised the design of more than 2000 others.

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