The full bridge converter (FBC) topology is widely used in mediumvoltage, high frequency 1kW to 10kW dcdc power supplies. A typical example is a 350V/5V power supply used in computers and telecommunication equipment. We use power metal oxide semiconductor field effect transistors (MOSFETs) rated at 400V to 600V/10A to 50A in the full bridge at the input of the converter. Operation of MOSFETs in a hardswitched FBC results in excessive device switching power loss — especially at high switching frequencies. Circuit and package parasitic inductances generally cause overvoltage stress. In addition, the MOSFET body diode may undergo stressful reverse recovery under certain switching conditions. The softswitched phaseshifted FBC (PSFBC) significantly reduces dynamic switching stresses and offers high power conversion efficiency, constant operating frequency, and good EMI characteristics. An advantage of PSFBC is the reduction of switching power loss with a similar circuit topology as the hardswitched FBC — but with a distinct control strategy. The PSFBC is popular for switchmode power supplies in this power range.
You can see the schematic circuit diagram of the PSFBC in Fig. 1. The switches M_{1} and M_{2} form the lagging leg and M_{3} and M_{4} form the leading leg of the bridge. Experimentally demonstrated, this is a wellestablished design procedure for this topology ^{[1]} .
You can see the current and voltage waveforms of the switches over one complete cycle in Fig. 2. Resonance between the output capacitance of the FET and circuit parasitics during the switching transients enables zero voltage switching (ZVS). The leakage inductance (L_{lk} ) of the transformer controls the switching of M_{3} and M_{4} , while the output filter inductor current reflected to the primary determines that of M_{1} and M_{2} . Hence, the waveforms of M_{3} and M_{4} are distinct from those of M_{1} and M_{2} . M_{3} and M_{4} don't conduct simultaneously, and their waveforms are similar over opposite halves of the switching cycle. The same is true for M_{1} and M_{2} .
During ZVS, the inductors must completely charge/discharge the voltagedependent output capacitors of both switches in a leg (leading or lagging) — as well as the transformer winding capacitance, C_{TR} . Accordingly, the minimum energy in L_{lk} and primary current (I_{2} ) required for soft switching in the leading leg are ^{[1]} :
Where:
C_{oe3} (C_{oe4} )=Effective output capacitance of M_{3} (M_{4} )=4 / 3 C_{oss}
Where:
C_{oss} =Output capacitance when V_{DS} =V_{IN}
If L_{lk} has less energy than E_{min} , the output capacitors are only partially charged/discharged. Turning the MOSFET on in this condition causes a Cdv/dt shootthrough current spike through the leg. This current surge in lowload conditions could lead to switch failure ^{[2]} . At energies higher than E_{min} , L_{lk} facilitates lossless energy transfer between the output capacitors of M_{3} and M_{4} . The energy stored in the output capacitor of each switch during turnoff recirculates into the circuit during turnon.
The output filter inductor has much higher energy than E_{min} . It charges and discharges the output capacitances of switches M_{1} and M_{2} approximately linearly. Thus, the ZVS operation of the leading leg is lost earlier than that of the lagging leg. Hence, developers must design the switching transitions of M_{3} and M_{4} carefully for a wide ZVS range.
The energy in L_{lk} increases rapidly at loads higher than the minimum load for ZVS. The voltage transition of M_{3} and M_{4} takes place with a nearly constant dv/dt since the current that charges or discharges the output capacitance increases at higher load levels. Assuming that the I_{2} splits equally between M_{3} and M_{4} , the corresponding dv/dt is given by:
The gate drives of power MOSFETs typically have a finite gate resistance (R_{G} ) that controls the transfer of gate charge to and from the input capacitance. Generally, the turnoff current through the power MOSFET has three components, as depicted in Fig. 3, on page 44. A dv/dt at the drain induces a current I_{Co} (=C_{oe} dv/dt) through the output capacitor and a current I_{Cf} (=C_{fe} dv/dt) through the feedback capacitor and the gate. Here, C_{fe} is the effective value of the voltagedependent feedback capacitor (C_{GD} ). A remaining current (I_{2} I_{Co} I_{Cf} ) flows through the FET channel. The gate current (I_{Cf} ) also flows through the gate resistor (R_{G} ) of the FET. At high load currents, the voltage drop across R_{G} places an upper limit on the dv/dt value. Thus,
Where:
V_{Gn} =Negative applied gate voltage
V_{GS,on} =Gatesource voltage (V_{GS} ) required to support the current I_{M} through the channel in saturation.
Current flow through the FET channel and gate resistance of M_{3} and M_{4} represents a “real” loss during switch turnoff. Turnoff energy increases with load current. Note, C_{oe} primarily determines the dv/dt at lowmedium loads.
Gate voltage is at its low level (V_{Gn} ) during the turnon transient. The energy in C_{oe} (and to a lesser extent C_{fe} ) recirculates into the circuit when the drain voltage falls. Since the channel doesn't support external current, C_{oe} almost entirely provides the turnon energy of the switch — with a value of 1/2C_{oe} V_{in}^{2} . Thus, the switch experiences ZVS turnon if the energy in L_{lk} is higher than E_{min} . The mismatch between the turnon and turnoff energies of the MOSFET results in switching loss at higher load current.
The body diode of the MOSFET conducts the inductor current at the end of the turnon transient. The MOSFET is turned on after a dead time equal to onefourth of the resonant period of L_{lk} with the switch output capacitance ^{[1]} . Once the switch turns on, the FET channel conducts reverse current in parallel with the body diode, as depicted in Fig. 4, page 47. The diode onstate conduction is modeled as V_{D} =V_{F} +I_{D} R_{D} , where V_{F} is the turnon voltage and R_{D} is the diode series resistance. With an FET onresistance of R_{M} , you can express the current through the diode as:
You express the voltage drop experienced during reverse conduction as V_{ON} =I_{D} R_{D} +(I_{2} I_{D} )R_{M} . Most of the reverse current flows through the FET channel during low load, the body diode primarily supports the reverse current during high load. After the zero crossing of switch current, all current flows through the FET channel and the voltage drop is simply given as I_{2} R_{M} . Since the FET channel current also flows through this lowresistance drift region, the value of R_{M} is lower than the value obtained from the output characteristics at the same current level. Excess charge in the body diode decays by recombination during forward conduction phase. Considerable charge also sweeps out during the turnoff transient, adding to turnoff power loss. Charge removal can lead to switch failure under high load conditions ^{[3]} .
Fig. 5 shows the influence of R_{G} and I_{2} on the conduction and overall switching energy losses per cycle of the switches M_{3} and M_{4} in a PSFBC. The converter operates at 75 kHz with L_{lk} =120μJ and V_{IN} =300V. The switches have ratings at 500V/20A. With measurements less than 2 μJ for the turnon energy of the switches, the turnoff process determines the overall switching energy loss — and it's much higher than the energy stored in the output capacitor alone. For a given FET, the choice of R_{G} also affects the turnoff loss. The switching loss is comparable to the conduction loss at the chosen switching frequency.
It's necessary to optimize power MOSFET technology to suit specific switching and reliability considerations in the application ^{[46]} . Last year, the Power Electronics Reliability Group (PERG), was founded for the development and commercialization of highperformance power supply technologies in the emerging Internet age ^{[7]} .
References

J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, “Design considerations for highvoltage highpower fullbridge zerovoltageswitched PWM converter,” in Proc. IEEE APEC, 1990, pp. 275284.

N. Keskar, M. Trivedi, and K. Shenai, “Device Reliability and Robust Power Converter Development,” Microelectronics Reliability, Vol. 39, No. 67, pp. 11211130, June 1999.

H. Aigner, K. Dierberger, and D. Grafham, “Improving the fullbridge phaseshift ZVT converter for failurefree operation under extreme conditions in welding and similar applications,” in Proc. IEEE IAS Ann. Mtg., 1998.

K. Shenai, “MadetoOrder Power,” IEEE Spectrum, Vol. 37, No. 7, pp. 5055, 2000.

K. Shenai, P. J. Singh, S. Rao, D. Sorenson, K. Chu, and G. Galyon, “On the Reliability of DCDC Power Converters,” Proc. IEEE IECEC, 2000, pp. 14801490.

K. Shenai, “Power Semiconductor Manufacturers Need to Update MOSFET SOA,” PCIM Magazine, Dec. 2000.
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