One “component” in the quest for improved energy efficiency and power quality is the use of active harmonic filter power factor correction (PFC) in switched-mode power supplies (SMPSs) for computing and industrial applications. Active PFC offers several well-known benefits, including automatic line-voltage adjustment, marked improvement of ac mains power quality in medium- and high-power applications, and stabilization of the SMPS bulk bus voltage. These features, in turn, improve cost factors and the holdup time of the isolated PWM converter.
Though the basic implementation of active PFC with a boost converter is topologically quite simple, the devil is in the details. One challenge is managing surge current at startup and during brownouts due to cycle skip. It's also difficult to achieve high efficiency and compact size simultaneously at higher power levels where continuous current mode (CCM) operation is preferred for the boost inductor because of the lower EMI and switch/diode stress associated with CCM.
To demonstrate how these various requirements may be met, a design example for a 650-W power supply will be presented using a new high-integration PFC controller for continuous conduction mode PFC. This controller will be combined with a very low switching loss superjunction MOSFET and a SiC Schottky diode in hard switching. The basis of this design, the ICE1PCS01 controller, is the first CCM PFC with enhanced protection and management features integrated into compact 8-pin DIP or SOIC.
This controller replaces other larger package types usually used for this application with no loss in functionality. The integration level of the ICE1PCS01 and the simplification of the PFC implementation are reflected in a simplified design process aided by an available XL design tool.
While the PFC boost converter is a simple topology in principle, the inherently wide range of operating input voltage (85 Vac to 265 Vac in this example) requires evaluation in the design process. In particular, the wide input range relates to stress factors such as brownout and cycle skip recovery, when switch and diode current max out. Simple calculations can be used to establish the basic operating conditions and component values. Using a calculation program like MathCAD makes it feasible to estimate the operating waveforms and losses based on the waveforms expected over the complete ac operating cycle. This analysis makes possible a more complete design synthesis in the first pass before building and testing hardware.
With this approach, we'll explore two variants on a 650-W PFC design. One version uses a 250-kHz clock to achieve component size reduction, while the other trades size for other benefits with a more typical 100-kHz version. Requirements for the proposed design are listed in the table.
About 10% extra power is budgeted to compensate for the efficiency loss of the PWM stage following the PFC boost converter. “Brownout” holdup voltage is the worst-case electrical performance required but not for sustained thermal capability. It also considers the requirement to provide full output power while charging/recharging the bulk bus cap (such as during cycle skip recovery). For this reason, we'll use 75 Vac as the effective low-line value for power limiting.
|Input voltage range||VINmin - VINmax||90 Vac to 265 Vac|
|Nominal output voltage||Vout||400 V|
|Rated output power to PWM||Pout||650 W|
|Target efficiency||h||92% +|
|Minimum bus operating voltage||VBUSmin||300 V|
|Inductor ripple current||IRipple||20% to 30% IPk|
|Operating pulse frequency||fS||250 kHz|
|Minimum holdup time||THoldup||20 msec|
|Line dropout voltage (effective min low line)||VIN_rms||75 Vac|
Passive Component/Rectifier Parameters
First, we'll estimate the peak input current based on Pout, target efficiency η, and VIN_rms,
Next, estimate dissipation of power rectifier for total loss calculation and heatsink sizing:
Calculate the thermal impedance to ambient RthHS required for power rectifier; assume maximum junction temperature TJmax = 150°C, maximum ambient temperature TAmax of 70°C, Junction to HS RthJHS = 2 K/W,
The boost inductor is sized based on the ripple current-to-line current ratio, which has a typical range of 20% to 30%. The inductance value depends on the chosen switching frequency and the tolerable current ripple. Space limitations preclude a detailed discussion of the tradeoff, but let's examine two possibilities: One will be at 100-kHz reflecting typical industry practice with standard semiconductor components, and the other will be at 250 kHz, which is easily achieved with superjunction MOSFETs and silicon carbide Schottky rectifiers.
The worst-case ripple current will be determined by the duty cycle of the switch at the peak voltage of low line and the clock frequency used. This won't be the point of highest duty cycle in the switch, but it will reflect the highest current and current ripple in the inductor.
Considering the basic input-to-output duty cycle (D) transfer function of the boost converter:
Then, calculate the duty cycle at the peak of the waveform (substituting root of 2, times the ac value) in the equation:
Next, the MOSFET tON time is calculated for fS = 250 kHz
And finally, estimate nominal inductor value as follows:
For 100-kHz, the inductance calculated is about 270 µH. How do these two inductors compare, using equivalent cores and design practices? Using standard methods for synthesizing SMPS inductor design, assume a no load-to-full load inductance/permeability drop of 30% to 40% with a powdered MPP core.
The realized design for 250 kHz uses a 55439-A2 core with 34 turns of two strands of AWG 15 wire, resulting in a net loaded inductance of ~108 µH, with a no load inductance of 165 µH, and estimated core losses of 2.4 W and copper losses of 3.6 W, for a total estimated loss of 6 W at a 75-Vac input. In contrast, the 270-µH 100-kHz inductor was realized with two stacked 55439-A2 cores and 38 turns of two strands of AWG 15, resulting in estimated core loss of 1.6 W, estimated copper loss of 7.5 W (including the effect of longer path length) and total estimated losses of 9.1 W.
This loss is almost 50% higher than that achieved with the 250-kHz 112-µH inductor. However, the argument for lower operating frequency usually is reduced losses with a focus on semiconductors. The inductor losses can be reduced, but only with a larger, more expensive construction. The issue for the designer, then, is how much the change in operating frequency affects the semiconductor losses and EMI filter, and if with the total losses the overall reduction in magnetics volume and cost is worthwhile.
The bulk capacitor selection process is driven primarily by the required ripple current capability, hold-up time requirements and operating voltage. For a nominal bulk bus of 400 V, a 450-V capacitor should provide adequate margin considering the overvoltage protection (OVP) response characteristics of the ICE1PCS01.
Holdup time is dependent on the range of bulk bus operation for the PWM isolation converter. The wider the range over which the converter can operate, the smaller the bulk capacitor possible. However, at the same time, this widening of input voltage range compromises the efficiency and transformer utilization of the output converter. A typical compromise might be an operating range extending down to 300 V. Then, the necessary value can be calculated:
The bulk capacitor was realized in the demonstration design using two 180-µF caps. This parallel combination of two capacitors provides a higher total ripple current rating and better cooling (from increased surface area) than would a single capacitor.
Boost Switch and Boost Rectifier
Estimating the operating conditions and losses for the boost switch and diode are difficult to do with any accuracy if only simplified expressions are used to define the operating conditions. In particular, the switching loss is dependent on instantaneous current and clock frequency.
To address this reality, the operating ripple current and pulse-by-pulse operation is calculated to estimate the total loss. These operating points are determined by the input voltage and current over one complete ac cycle. First, functions specifying the ac operating period and the input voltage and an indexed variable for the period are defined as:
Using the previously calculated values for RMS input current, a waveform for the PFC input current is calculated:
Next, taking a data point at one quarter of the ac period interval should yield the peak input current:
Iin_max = 13.93 A (12)
This agrees with the value calculated in equation (1). Using the same range variables, the duty cycle for the switch and diode can be calculated and plotted (see Fig. 1) over one ac mains period:
Next, the ripple current ΔI as a function of input voltage and operating duty cycle is calculated for the on time (switch) and off time (diode):
A plot of the estimated minimum and maximum inductor current for 110 µH inductor and 250- kHz switching frequency is shown in Fig. 2. These are the currents which have to be handled by the boost switch and boost rectifier. The average and RMS switch current can be calculated by integration (see Fig. 3):
Waveforms of maximum and minimum switch current peak current are used to determine the switching losses:
Then the switch conduction losses can be calculated, considering the RON, conduction time and current:
Integration of momentary values gives average conduction losses.
Switching Losses in MOSFET
Using data that is also incorporated in the data sheets regarding switching loss behavior for turn-on (Eon) and turn-off (Eoff), and switching behavior as a function of gate resistance and load current, functions have been defined in MathCAD, which calculate the turn-on and turn-off losses in joules per switching event (space limitations preclude including full details here).
These switching event losses are multiplied based on the SMPS switching frequency to calculate the total loss. Switching loss behavior in superjunction MOSFETs such as CoolMOS is often much lower than for conventional vertical DMOS transistors because of the effect of the nonlinear output capacitance, which acts as a nonlinear snubber capacitor, reducing turn-off losses over those expected.
Integration gives the average turn-on losses:
The turn-off calculation is a complex function of current amplitude, RG and device type, which isn't shown in detail here for space limitations:
In comparison, at 100 kHz the turn-on losses are estimated at 1.3 W and turn-off at 3 W. This amounts to a difference of ~7 W, partially offset by lower inductor losses by 3 W.
Combining conduction and switching power losses in the boost switch (see Fig. 4):
Conduction and Switching Losses in Diode
The peak diode currents, of course, are at the same amplitude as the peak switch currents. Considering the average and RMS values, some care should be taken because of the high crest factor of peak current to average current in the boost rectifier. Under surge conditions as when recovering from cycle skip, the duty cycle ratios can flip while very high peak current exits in the diode. This action raises the surge power dissipation dramatically for up to several ac mains cycles unless protective measures are taken by the controller.
The diode conduction losses depend on the forward characteristic of the diode, which must be considered in the loss calculation. The silicon carbide Schottky rectifier can be modeled as a junction potential with a negative temperature coefficient combined with a drift region resistance with a positive temperature coefficient. The operating waveform of diode current can be calculated over one ac mains period as follows:
The average and RMS current are then calculated by integration:
Next, minimum and maximum diode currents can be calculated over one mains period:
The instantaneous conduction loss is calculated from:
From integration of the results of this function the averaged loss over the mains period is calculated:
Diode Switching Loss
In the case of conventional ultrafast silicon diodes, calculating the switching losses is quite complex, if possible at all, due to the several nonlinear effects on Qrr behavior. These effects include rising effective Qrr with rising di/dt and rising temperature. For SiC Schottky diodes, the matter is greatly simplified, as there is no Qrr per se, only a displacement charge exists due to the depletion capacitance, for which loss is easily estimated per switching cycle.[4, 5, 6]
For the proposed 6-A SiC Schottky rectifier:
In comparison, at 100 kHz, the estimated turn-off losses are 0.42 W, not a significant difference.
Then the total power losses in the boost diode are the sum of conduction and switching loss:
PD: = PD_cond_avg + PD_off PD = 6.897W
Heatsink calculations for the boost switch and diode must account for the thermal interface material between the transistor and diode package and the heatsink. This varies by type, but for popular TO-220 materials it's in the range of 1.5 K/W, and for the TO-247 package, the greater area yields about 1 K/W. If one uses a maximum ambient of 50°C and a maximum junction temperature target of 130°C, for conservative derating practice, the heatsink to ambient impedance follows:
At this thermal impedance, forced air flow will make a substantial size reduction possible for the heatsink. With different requirements for junction temperature or ambient, the parameters can be modified accordingly. The diode heatsink requirements can be calculated similarly:
Calculation of Other Component Parameters
The ICE1PCS01 PFC controller integrates functions for soft-start, open-loop protection, brownout protection, enhanced dynamic loop response, soft and hard overcurrent protection . It operates with duty cycle capability exceeding 95% and can be used over a wide switching frequency range, up to 250 kHz. The built-in totem pole driver can supply up to 1.5 A for driving a MOSFET or IGBT boost switch.
Only a few external parts are required to define functionality for the output voltage set point, operating frequency, maximum power output, soft-start, voltage control loop bandwidth and average mode current loop (Fig. 5). Components to determine include the current sense resistor, the frequency setting resistor, the average current mode compensation and the voltage loop compensation.
The compensation network design for a PFC controller is critical because of the influence on main performance areas, including loop transient response, THD for input current and the net power factor. The maximum average input current, Iin_max, was previously calculated in equation 12. However, for the current-sense resistor calculation the effect of inductor ripple current, as shown in Fig. 2, must be used. Considering the soft limiting threshold of 700 mV for the current sense input to determine the maximum output power, the current sense resistor value is found from:
The current sense resistor should be a low-inductance type. Paralleled high-current surface-mount devices (SMDs) work better in this application than axial-leaded resistors because of the much lower inductance of the SMDs. In the design shown, SMD resistors were paralleled with a slightly lower resistance than the calculated value, as this is offset by the PCB trace resistance.
Because a high surge current and voltage drop across this resistor can be generated at initial charge of the bulk capacitor, it's required to include a series resistor of ~200 Ω on the current sense pin to prevent damage from excess voltage to the ISENSE input.
The current loop is controlled by a transconductance amplifier OTA2, which has two inputs: a signal from the nonlinear gain block and a signal from the current-sense pin. The main variable from a design viewpoint is the switching frequency of the converter. Due to the influence of the nonlinear gain block, it is necessary to add an additional capacitance in the range of 0.5 nF to the calculated value:
Output voltage setting (feedback loop) is determined by the internal VREF and R17 and
R11+R12 externally; targeting 400 V, and assuming a value of 5.11 kO for the shunt resistor R17,
RSeries is split into two resistors R11 and R12 for reason of power handling and voltage withstanding; two 201K 1% resistors are suggested. This yields a calculated output of
The feedback signal from the output voltage divider is fed to OTA1 at pin 6 (VSENSE). OTA1 is a transconductance amplifier and charges the compensation network at VCOMP pin 5, consisting of R23, C11 and C20. Note that this current charge rate into the compensation network also determines the soft-start time.
The output voltage at the bulk bus capacitors C18 and C22 contains a ripple voltage at double the frequency of the lines voltage from the current fed through the boost rectifier (Fig. 3). The voltage-loop compensation must be set so that this ripple is not amplified through the control loop. Instead, it should be well suppressed, by setting the error amp loop gain to unity in the neighborhood of one-tenth the mains frequency. For stability reasons, a phase lead is used to improve the phase margin. The chosen values for R23, C11 and C20 are shown in Fig. 5.
C11 = 1 × 10-7
C20 = 1 × 10-6
R23 = 1 × 104
The response of combination of OTA1 Vcomp output (with nominal GOTA1 = 40 µS or microsiemens) can be described for the frequency dependent variable S jω :
and the phase in degrees of this function calculated from this equation in MathCAD:
The amplitude and phase transfer function are shown in Fig. 6, which shows a nominal loop bandwidth of ~6 Hz and ~20° phase margin.
IC Protection Functionality
The key to operational robustness, in addition to sizing the active and passive components correctly, is the protection and startup control functions of the controller. These functions have been designed according to failure mode error analysis (FMEA) and are managed by the inputs from just a few pins. Specifically, those pins are VSENSE, ISENSE and VCC, with VCOMP used to set loop compensation and manage soft-start-related protection functions. (For a basic state diagram, see Application Note AN-PFC-ICE1PCS01-1, available at www.infineon.com.)
There are several off-state modes related both to safe startup conditions and protective shutdown. These include:
OFF — before VCC reaches 11 V or when VCC drops below 10 V (UVLO)
OFF — if VSENSE is below 0.8 V, due to external pull down (standby mode), VIN does not reach VIN(MIN) (undervoltage protection or UVP), or open loop protection (OLP), loss of feedback connection
OFF — if VOUT drops below 50% of rated voltage (brownout protection or BOP) with ISENSE ~0.7 V
OFF — when peak current limit is exceeded (peak current limit or PCL) — ISENSE > 1.05 V
OFF — if VOUT is higher than 105% VOUT(NOM) (overvoltage protection or OVP).
The basic soft-start functionality is used in several modes, including power limiting while maintaining sinusoidal current during the initial turn-on while VSENSE>0.8 V and <4 V. In the case of output overload, when the ISENSE pin reaches -0.7 V, the soft overcurrent (SOC) function reduces the current-loop gain, limiting the maximum output power.
Should the output voltage decline below 51% of rated value, which is 2.55 V at the VSENSE pin, the soft-start cycle is reset and a new startup will be attempted. SOC limiting is not a cycle- by-cycle limit but maintains the sinusoidal current wave shape. Peak current limiting on a cycle-by-cycle basis is implemented only if the ISENSE pin exceeds -1.08 V.
An Excel tool has been created to make many of the calculations described above for designing a converter. This tool features user-input fields for converter specifications, drop down boxes for standard component value selection and predefined parameters for some popular cores. The Excel tool can be obtained from www.infineon.com.
A dual-layer version of the test board was constructed with the calculated components, as shown in the schematic of Fig. 5. Layout practices used a minimal size for the HF current loop between C17 and C16, and Q2 and D9. The performance was as expected from the design calculations, and the measured efficiency at 600 W out over the line-voltage range is shown in Fig. 7.
Measurements showed that the rise and fall time of Q2 was limited somewhat by the 1.5-A gate drive booster in the ICE1PCS01, and overall efficiency might be improved slightly by using a gate drive booster. The results in switching efficiency were comparable to those achieved at both higher and lower powers for these components in similar applications.[9,10]
Magnetics Inc., “Inductor Design in Switching Regulators,” Technical Bulletin SR-1A.
Infineon Technologies, “ICEPCS01 — Standalone Power Factor Correction Controller in Continuous Conduction Mode,” Datasheet May 2003.
Wei Dong, Bing Lu, Qun Zhao and Fred C. Lee, “Performance Evaluation of CoolMOS TM and SiC Diode for PFC Applications,” APEC 2004.
R. Rupp, M. Treu, A. Mauder, E. Griebl, W. Werner, W. Bartsch, D. Stephani, “Performance and Reliability Issues of SiC-Schottky Diodes,” presented at International Conference on SiC and Reliability Comp '99.
H. Kapels, R. Rupp, L. Lorenz, I. Zverev, “SiC Schottky diodes: A Milestone in hard switching applications,” Proceedings, PCIM 2001, Nuremberg, Germany, 2001.
I. Zverev, H. Kapels, R. Rupp, M. Herfurth, Silicon Carbide Schottky: “Novel Devices Require Novel Design Rules,” PCIM 2002 Proceedings, Nuremberg, Germany.
W. Frank, “ICE1PCS01 — Technical Description,” Application Note, Infineon Technologies AG, Munich, Germany; Feb. 2003.
W. Frank, “ICE1PCS01 — Calculation Tool for PFC Preconverter using ICE1PCS01,” Application Note, Infineon Technologies AG, Munich, Germany, 2002.
J. Hancock, L. Lorenz, “Comparison of Circuit Design Approaches in High Frequency PFC Converters for SiC Schottky Diode and High Performance Silicon Diodes,” PCIM 2001 Proc., pp. 192-200.
Staff, “First Mass-Produced Power Supplies Featuring SiC Diodes,” Power Electronics Europe, April 2004.
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