Power Electronics

Shunt Regulator Design Enhances LDO Reliability

Unlike high-current LDOs that rely on series regulator techniques, a discrete LDO design based on a shunt regulator offers foldback current limiting and fast transient response.

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With complex processor chips and processor-based systems proliferating rapidly, the demand for fast transient response, lower noise and less complex dc power supplies poses major challenges for power supply designers. Some applications now require adequate transient response in the face of fast-varying dynamic loads with transients of 100 A/µsec to 1000 A/µec at 3.3 V output or lower. Such demands have helped low dropout regulators (LDOs) to find a reasonable share of the voltage regulator IC market.[1]

On some occasions, an LDO is used to power a specific part on an overall circuit, where the bulk dc is derived by a switching supply.[2] In many portable appliances where battery power is primarily used, LDOs are used to achieve extremely low dropout voltages and, hence, conserve power.

When efficiency and compactness come first, designers tend to select a switching regulator module for many dc power supply needs. However, due to energy-storage elements, such as inductors and capacitors inside the circuits, these can have low response times, high RFI/EMI, and other complications when the difference between the unregulated input and the regulated output can be minimal. In such situations, LDO regulators provide better overall solutions or work nicely in tandem with a switched-mode power supply (SMPS) module.

An LDO is generally based on a linear series regulator technique where the unregulated voltage is buffered by a series transistor element, such as an NPN or PNP bipolar junction transistor (BJT), or a MOSFET, with a suitable feedback loop to maintain the output voltage at the required value. In many situations, the dropout voltage is on the order of 0.1 V to 2 V with the control circuits using extremely low power, providing efficiencies around 65% and even higher for lower dropout voltages. Another useful application of the LDOs is in automotive environments, where the battery terminal voltage can fall much below its nominal 12-V value during engine cranking and other operations.[3]

LDOs based on the series-regulator concept provide adequate transient response for fast-varying loads. However, one design problem with these LDOs is the need for proper compensation.[4]

Deviating from the series-regulator approach, the shunt-regulator technique described here has the added advantage of foldback-current limiting. This discretely implemented LDO, which requires few components to implement, also provides fast transient response.

Using a power MOSFET as a dropper element and a BJT for voltage regulation, a high-current VRM can be developed using inexpensive discrete components (Fig. 1). The technique can be suitable for applications where the load frequently draws its maximum current and has the tendency for short circuits or overloads. The technique can easily be adopted for 1.2-V to 3.3-V output power rails delivering load currents from a few milliamps to over 10 A.

Shunt Regulation Concept

The circuit in this voltage regulation topology is based on a previously described shunt-regulated dc-power-supply technique.[5, 6, 7] With this technique, a reference voltage is compared with a sample of the power supply output voltage, which is derived from a voltage divider in the feedback loop. A series transistor element acts as a constant-current source, while a shunt transistor acts as the regulating element. When the load current fluctuates, the shunt transistor acts as a current shunt, allowing output-voltage regulation during fast transients.

A bipolar transistor or a MOSFET configured to act as a current source — or a variable resistance — receives its control from the collector load path of a differential pair transistor. Under normal operation, within the set value of the output current limit, the collector current of the differential pair transistor provides sufficient voltage at its collector to maintain the current source value, setting the maximum current limit of the regulator module. This configuration not only permits the setting of a maximum load current limit but also achieves foldback-current limiting.

During overload conditions, foldback-current limiting is achieved by changing the voltage at the collector of the differential pair transistor. When the load attempts drawing a current beyond the set regulation limit, such as a case of a short-circuited output, the voltage output drops below the regulation limit and the base voltage of the differential pair transistor drops, forcing it to operate in the cut-off region.

Applying the Concept to LDOs

The shunt-regulator topology meets the fundamental requirement of an LDO, which is to have a low dropout voltage between the input and the output, while also permitting foldback-current limiting. For example, if one needs a voltage regulator module with an input of around 3.5 V to 5.2 V, with the output operating at 3.3 V or even lower, this topology is practical, particularly for cases where the load draws close to the maximum current most of the time. This makes the dissipation in the shunt-regulating element pretty low. At the same time, a MOSFET can be used to take up the dropout voltage to perform foldback-current limiting.

In series regulators, to achieve foldback- or constant-current limiting, a series resistor is necessary in the load path to activate the protection. Most series regulator LDOs generally use constant-current limiting for overload protection.[8] In general, a series regulator has a tendency to overheat the series transistor element during an output short circuit or an overload condition. This occurs because the series element is subjected to the maximum voltage difference across the emitter and collector.

Foldback-current limiting substantially reduces power dissipation within the regulator during an overload while safeguarding the load. It simultaneously reduces the load current as well as the input supply current, increasing reliability.[8] In this particular shunt-regulator technique, no additional current-monitoring resistor is needed. This eliminates the need for high-current capable resistors or the use of special pc-board tracks for the activation of current limiting.

Fig. 1 indicates the basic approach to designing an LDO version of the shunt regulator. In the case where the output is 3.3 V and the input is as low as 3.5 V, it is easiest to use a MOSFET as the dropper element and have a charge pump output to supply the gate-source voltage drive. Any suitable voltage reference source could be used to provide the reference voltage (VREF) to the differential pair (Q1 and Q2), which compares the sample of the output voltage with the reference voltage. To provide a reasonably preregulated voltage to the differential pair, the same reference source could be used.

A charge pump (VCP) provides sufficient voltage to drive the gate-source voltage of Q4 via the opto-isolator transistor, which gets biased into conduction when both transistors in the differential pair operate in the active region. This keeps the MOSFET in conduction, allowing sufficient current to the shunt element (Q3) and the load, setting the maximum current limit.

As depicted in Fig. 1, the PNP shunt element Q3 receives its base current from the collector of the differential pair transistor Q2, maintaining the simplified relationship:

MOSFET Q4 acts as current source taking up the dropout voltage (VIN-VOUT) between the drain and the source terminals. When the MOSFET operates in the triode region where VDS ≤ VGS-VT , the approximate drain current (IM) is given by:

IM=k(VIN-VOUT)(VGS-V T)

(Eq. 2)

For operation in the saturation region of a MOSFET, where VDS > VGS-VT:

IM=0.5k(VGS-VT)2

(Eq. 3)

Where VGS is the gate-source voltage, VT is the gate-source threshold voltage and k is a constant for the device based on the fabrication details.

For lower values of VGS, the MOSFET acts as a linear resistance, but under conditions in Eq. 3 it operates in saturation. The second case can easily be used to set the maximum current value for the load.

In Fig. 1, Q4 receives its gate-source voltage VGS from the charge pump's output in series with the output transistor stage of an optocoupler. Under normal operation, when the load current is below the maximum set limit (IM), the collector current of the transistor Q2 develops sufficient voltage across Rz to keep the diode of the optoisolator biased, so that the effective impedance of the output optotransistor is low enough to supply sufficient gate-source voltage to Q4. This configuration allows setting the maximum load current limit, after which foldback-current limiting occurs. While the load current fluctuates within the maximum set limit IM, the transistor Q3 acts as a current shunt, allowing output-voltage regulation during fast transients.

A practical implementation of the concept depicted in Fig. 1 is shown in Fig. 2. In this example, a 3.3-V output regulator operates from an input range of 4 V to greater than 6.5 V with a current limit adjustable up to 5 A. This circuit provides a foldback limit condition with a substantially lower short-circuit current determined by the quiescent consumption of the control circuits.

Q3 and Q4 form the shunt-transistor element, where the base is connected to the collector output of the Q2 transistor of the differential pair Q1 and Q2. The base of Q1 is fed from a 2.5-V reference voltage derived from the reference source (U1), which powers the charge pump formed by Q5, Q6 and Q7. The reference derived from U1 develops a charge pump output around 7.5 V, which supplies the gate-source voltage to the MOSFET via the opto-isolator's output transistor.

Fig.3a depicts the output regulation characteristics of the LDO at different maximum current settings achieved by adjusting the variable resistor R3 in Fig. 2. The short-circuit current of the circuit when foldback occurs is less than 70 mA, which was within a targeted design limit of 5% of the maximum load current. Fig. 3b indicates the line regulation characteristics of the circuit. The transient response of the circuit is depicted in Fig. 4 when the maximum output current limit is set to 2 A.

One obvious problem of a shunt regulator is that the shunt transistor takes up the maximum set current when the load consumes nearly zero condition. This forces the shunt transistor to be provided with an adequate heatsink. However, by using a few additional circuit blocks, as depicted in Fig. 5, the problem can be minimized.

In this particular case, the current through the shunt element is monitored, and this is used in a feedback arrangement using an optocoupler to adjust VGS of M1. A photovoltaic isolator, such as PVI5050, biased through Q3 and Q4 is used to supply VGS to M1. An overload condition will remove the bias current to Q3, which in turn will remove bias current to the PVI and activate foldback-current limiting.

The speed of the foldback-current limiting is controlled by the time constant of R9C3. Performance of the resulting circuit is shown in Figs. 6 and 7, and the transient performance is shown in Fig. 8.

Performance Comparison

Table 1 compares the measured performance of the two shunt regulator-based LDO designs with the published performance data for two typical, commercially available monolithic LDOs — the ADP3339 and the LMS1282A. Note that these are not direct comparisons given the differences in electrical specifications.

As indicated in the table, the approach used in Fig. 5 compared to the circuit topology in Fig. 2, helps reduce the need for heatsinks for the case where load current switches back and forth from minimum to maximum. The two shunt regulator circuit examples were not optimized to minimize short-circuit currents. Nevertheless, both circuits clearly minimize the possible heating from short-circuit currents when compared with the series-type LDOs. Note also that these proof-of-concept circuits were not optimized for best line regulation.

Table 1. Comparison of shunt-regulator LDO designs with series regulator-based LDOs.
Parameter Fig. 2 Design Fig. 5 Design ADP3339 LMS1282A
Output Voltage (V) 3.3 3.3 1.8, 2.5, 2.85, 3.3, 5 3.3, 1.5
Max. output current (A) 5 2.3 1.5 5
Output-voltage tolerance 0.6% 0.8% 1.9% 0.5%
Line regulation 0.7% 0.9% 0.04 mV/V 0.2%
Load regulation 0.6% 0.4% 0.04 mV/mA 0.5%
Dropout voltage 1 V 0.4 V* 0.480 mV 1.4 V
No load current 5.2 A 100 mA 125 µA 13 mA
Short-circuit current 0 A** 500 mA 1 A 6.6 A
*Measured at 1-A load;
**Less than 140 mA drawn from unregulated input.


One important characteristic of these shunt-type topologies is that under short-circuit situations, current drawn from the unregulated input will be much smaller than the maximum designed load current, which is due to the foldback-limiting capability. The circuit topologies also can be tuned to perform better under extreme dropout cases, such as 0.2-V to 0.4-V situations common in industry applications. Toward that end, further work is in progress.

The shunt-regulation approach to LDO design may be worth pursuing in the development of LDOs that meet specific industry requirements. The research work clearly indicates that the technique can be further developed to perform under worst-case scenarios. Anyone interested in collaborating on shunt regulator design may contact the authors at [email protected].

Acknowledgment

The authors are grateful to the summer student research grant made available by the Department of Electrical and Computer Engineering of the University of Auckland, New Zealand.

References

  1. “Power Supply IC Market Will Double by Year 2003,” PCIM Power Electronic Systems, March 1999, p. 10.

  2. Travis, Bill. “Linear Versus Switching Supplies: Weighing All Options,” EDN, Jan. 1, 1998.

  3. Ciscato, S. “Low Dropout Voltage Regulators Survive in the Automotive Environment,” PCIM, June 1997, pp. 10-28.

  4. Simpson, C. “LDO Regulators Require Proper Compensation,” Electronic Design, Nov. 4, 1996, pp. 99-104.

  5. Kularatna, A.D.V.N. “A Variable Shunt Regulated Power Supply,” Electronic Engineering, UK, June 1978, p. 21.

  6. Kularatna, A.D.V.N. “Optosensor Limits Shunt Supply's No Load Current,” Electronics, McGraw-Hill (USA), Jan. 13, 1981, pp. 174-175.

  7. Kularatna, A.D.V.N. “Foldback Limiter Protects High Current Regulators,” Electronics, McGraw-Hill (USA), January 1980, p. 98.

  8. Peltier, W. and Goder, D. “Current Limiting Diffuses the DC/DC Time Bombs,” EDN, April 9, 1998.


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