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Lowering costs for new power management devices is a good reason for trying new approaches in the semiconductor industry. One approach is to try to significantly reduce the number of device tests during the production of a particular power integrated circuit. Each test that can be eliminated saves money and reduces the wafer start-to-customer delivery cycle-time. Device testing is essential to ensure the highest possible quality is delivered to customers; however, a test at every production step is unnecessary.
A final test is the minimum requirement to guarantee quality of the materials produced. Trimming at the final test has many advantages. Parameters that would normally be trimmed or programmed during the wafer probe test are now being directly adjusted or corrected on the packaged unit itself. These could be reference voltage (VREF), output voltage, current capability, gain-setting, shut-down features, timing settings, etc. These parameters can be configured by programming designated bits in an internal programmable memory such as EEPROM.
Currently, devices are designed to manage present requirements as well as future needs. An example of this concept is output voltage. A device's output voltages are determined by market demand. However, markets may change and new voltage ranges may be required. Designing devices with selectively different output voltages offers big advantages.
Other programmable parameters (current limits, timings) may open opportunities with new customers because tailor-made products could be delivered in a relatively short time. Finally, new devices do not need to be developed because this approach primarily relies on potential features of current devices.
Often, an entire IC product family is designed with devices varying only according to parameters such as output voltage, current capability, current limit and start-up functionality. In that case, all members of the device family have one property in common — they are all generated from an identical bare die. Programming gives the device its individual characteristics or behavior. This can be done after assembly at the final test. Die-banking is a favorable option that many semiconductor companies are pursuing.
Carrying one type of wafer in stock to assemble-on-demand is much easier than stocking different types of devices belonging to a same family. Presently, and in tight production times, this offers significant advantages to a semiconductor company.
Several versions of a wafer are released to market as a first step. These cover all versions that are supposed to gain market share and generate revenues. If market changes or customers require the same functionality with slightly different parameters (i.e., output voltage or current limit), these new devices can be produced quickly using the device's final-test trimming capability. This saves time (wafer fab cycle-time) and expedites availability of new versions. Only assembly time plus final-test (trim) cycle time is needed, which is less than half of a device's full cycle time (wafer fab, assembly and final test).
Trimming during final test also is beneficial because it takes into account any manufacturing variations that may occur. In some cases, it can reduce process parameter variations (i.e., bandgap reference voltage). Most of these parameters like VREF vary according to a standard normal distribution (gaussian distribution).
By trimming at final test, the distribution is limited or very “narrow.” The more bits used for trimming, the narrower the distribution of the measured parametric data; thus, the yield is higher for that specific parameter. As mentioned, this also takes assembly shifts into account. With probe trim, you must plan ahead for some assembly spread in the distribution of a certain parameter.
Most ICs must be trimmed accurately to meet the strict specification limits defined for the device. If the device is trimmed at probe test and then assembled and packaged, there may be a slight shift in a specific parameter. Fig. 1 shows a typically packaged device with its components.
Package stress is a typical occurrence that causes device failures or parameter shifts. Package-induced stress originates from the mismatch of the thermal expansion coefficients of the materials, as well as the fact that the materials are all combined at temperatures other than room temperature. Additionally, different mold compounds can exert different stress levels and, therefore, different device parametric shifts.
The package-induced stress may affect the device either through piezoresitive effects or by direct physical damage to the die. In the first case, the piezoresitive property of silicon can cause resistive changes, which in turn result in parameter shifts. Specifications that may be affected include reference voltage (bandgap); amplifier off-set voltage, comparator threshold voltage, current limit thresholds, oscillator frequency, delay times, and data converter linearity or bit weight. Or, package-induced stress can cause physical damage on the chip's surface, usually resulting in failures such as shorts or leakages.
|Bits 3 - 0||VREF adjust|
Because the assembly process can vary unpredictably over time, pressure, temperature and other variables, the probe test needs to account for a spread of distribution for the trimmed parameters. This uncertainty can be eliminated by trimming after the assembly process.
Programming EEPROM to Trim Parameters
If a reference voltage or a buffered band-gap voltage is accessible from a device pin, it can be easily measured to determine the impact of trimming this parameter. Assuming it is used only for internal purposes, the bandgap must be verified using a parameter such as output voltage, which is derived from the reference.
The fixed number of bits required to set a parameter to the designated target value determines whether there will be a wide trim range offering medium accuracy or a narrow trim range with high accuracy. The TPS65130, a switch-mode dc-dc converter with positive and negative output voltages, uses the scheme in the table to trim the bandgap to the target voltage of 1.213 V. This scheme gives step widths of approximately 4 mV to adjust the bandgap to its target value.
To allow trim steps in positive and negative direction, the default EEPROM bit setting is 1000, which is centered within the table. For this value, the bandgap is designed to show its best performance with respect to temperature coefficient and long-term stability.
Verifying the bandgap reference is an iterative process. The designated EEPROM bits are set to the default value (1000 in this example) before the VREF is measured. Based on the reading and trim schemes, the test program determines whether the VREF can achieve a value closer to the target voltage by reprogramming and remeasuring. Because programming the EEPROM takes some time (>10 ms), remember to trim the settings of recent devices and use their average as probably best “guess” for the next device's initial programming. An indirect way to verify the VREF (bandgap) is necessary if the voltage is not available on a device pin, due to pin-count constraints or if it is used for internal purposes only.
Testing the bandgap is done by adding test transistors (TM1 and TM2 in Fig. 2) into the device for easier and less-complicated device testing. Once the bandgap (VREF) voltage is measured, it is used for the trimming procedure as described above.
The bandgap voltage can be measured in either a closed-loop or open-loop manner. When the device-specific test feature is activated and test transistor TM1 is closed, the bandgap comparator becomes a buffer (Fig. 3). Now, the output of the comparator (VREF) can be directly measured at the input. In this case, the measurement is taken at the “FB” pin.
Another method of testing the bandgap is by keeping the comparator in open loop (Fig. 4). Here, another test transistor is closed (TM2) and the output of the comparator is routed as a digital pin to another device pin (LBO/TM output). Then, a ramp is applied to the input pin (FB), and the TM output is monitored for a logic-high. This transistion is then directly correlated back to the ramped voltage on the FB pin, indicating the value of VREF.
In general, temperature influences device parameters. When devices must operate over a wide temperature range in their target applications, correctly selecting the temperature to trim the device is essential. Trimming gives the best parameter performance for the device at the selected temperature. However, the device will eventually need to be trimmed-off at the best trim value for the device's specification under all operating conditions (supply voltage and temperature range). The normal temperature dependency of a bandgap is a positive temperature coefficient when “cold” and a negative one when “hot.”
A typical curvature of an untrimmed bandgap is shown in Fig. 5, curve (1). Assuming the bandgap is trimmed at wafer probe at a temperature of 85°C and then tested at final test at 25°C, the following effects may occur. Around room temperature (25°C), temperature coefficients of about 20 ppm/°C to 30 ppm/°C are attainable, but over a broad temperature spectrum (-55°C to 125°C), a shift of up to -1% is normal at cold and hot temperatures.
Bandgaps usually are trimmed to their ideal voltages to provide a low and stable temperature coefficient. The ideal voltage can be predetermined by theoretical considerations and mainly depends on physical constants. This also gives good long-term stability.
For perfect trim, the target voltage for the bandgap and the temperature must be well known. Bandgaps typically are trimmed by adjusting the output voltage by an amount proportional to absolute temperature (PTAT). This trimming assumes that when the reference voltage is 20 mV above nominal at 125°C (see curve (3) in Fig. 5), VREF will only increase by 11 mV at -55°C. If the bandgap is trimmed to an ideal value of 1.26 V at 25°C (see curve (2) in Fig. 5), the resulting band will be a voltage of 1.25 V at -55°C and 125°C. If the bandgap target voltage is not trimmed at the corresponding temperature after device packaging, then the temperature dependency could be worse even post-trim.
Skipping the probe test has certain risks that may affect the overall device yield. Assume packaged units are assembled from unprobed wafers. In that case, if the wafer process yield is low due to process problems, then bad units are assembled, thereby generating extra costs. The lower the yield, the higher the amount of extra, unnecessary costs used for the assembly of the unwanted units. Using wafer fab processes that are stable and generating high yields (>95%) provides the best opportunity to skip the probe test and assemble from unprobed wafers.
A rough estimation is illustrated in Fig. 6, which charts the test-time savings versus final-test yield. This graph assumes the units are tested only once — at final test — and that a virtual probe test would consume equal test-time per die. The data shown assumes a lot of 25 wafers with 10,000 dies per wafer and a probe test time per die of 250 ms. For a 100% yield, the total virtual probe test time is approximately 17.5 hr.
If the final-test yield drops to 95%, then each wafer will have 500 “bad” dies on it. Assembling all of these “bad” dies (25 wafers × 500 dies/wafer = 12,500 dies) of the unprobed wafer lot and retesting these packaged parts at final test will consume 0.9 hr of test time.
However, in return for the 0.9 hr of additional test time at final test, there is a savings of 16.6 hr of test time at wafer probe. That savings must be weighed against the added cost of assembling 12,500 “bad” dies. In addition, this calculation does not include costs for probe hardware, as these are fixed costs, compared to the costs for operation. Therefore, to benefit from skipping the probe test demands robust design for six-sigma quality, and accounting for the total costs of assembly per-die, the probe-test system costs and the possibility of verifying all parameters at final test.
In general, the engineer and design team should analyze each individual case to identify which of the previous recommendations should be implemented. The methods described can improve certain device parameters, shortening cycle times and saving assembly and test costs. With the rapid pace at which the semiconductor market is moving, these improvements and savings are extremely enticing to many device users and may lead to huge successes for them.
The Design of Band-Gap Reference Circuits: Trials and Tribulations. National Semiconductor. www.national.com/rap/Application/0,1570,24,00.html.
Nadler, Walter and Constantopoulos, John. DFT — The Easier Way to Test Analog ICs. Texas Instruments. www.techonline.com/community/ed_resource/feature_article/29722.
Nadler, Walter and Constantopoulos, John. Testmodi bei DC/DC-Schaltreglern. Texas Instruments. www.publish-industry.net/page-index/emvonline/redaktion/fachbeitraege/DV044401.html.