Power Electronics

Packaging Can Take Us Into Uncharted Territories

It's as old as the three-terminal voltage regulator or as new as the latest digital power controller. It's big and bulky or tiny and sleek. A few thick wires just out from its sides, or a matrix of tightly spaced pads or microspheres cling to its underbelly.

For identification, it uses alpha-numeric acronyms, some so arcane that few users probably remember what they originally stood for, and which are by now so familiar that the full names no longer matter. It also uses newer names consisting of acronyms that are more widely understood. Nonetheless, even the newer terms can be confusing, especially when different terms (often trademarked names) are applied to similar things.

By itself, it's not sufficient to build the simplest of circuits, yet without it, few systems would function. And electrical and thermal performance, manufacturability and reliability all depend on its successful application.

Of course, the “it” I am referring to is IC packaging, specifically the variety associated with power circuits. It's an eclectic subject to be sure. One that encompasses multiple engineering disciplines, ranging from the electrical and mechanical to material science and quality assurance.

Like the circuits they house, power IC packages are inherently analog creatures with all sorts of non-ideal characteristics and tolerances that chip developers and system designers must grapple with. And just as analog circuit design is often viewed as a “black art,” I'm sure many view IC package design as a somewhat mysterious craft.

Fortunately, system designers can often ignore the underlying complexities and treat IC packages as black boxes (which they may literally be). From an electrical standpoint, packaging effects are typically lumped in with the circuit parameters on the data sheet.

That said, power-system designers can ignore packaging technology at their peril. The technology is constantly evolving, the options only seem to multiply and those who overlook IC packaging advances ultimately may risk losing a competitive edge. At the very least, system designers need to be aware of advanced packaging options and ask themselves whether they might gain some advantage by adopting high-tech packaging.

These are a few issues to ponder as you unfold the 2008 Power IC Packaging Wallchart that's tucked into this issue. Don't be confused by the 2008 designation. We haven't done a 2007 version or any other that I know of. The year is simply there as a reminder that the chart represents a snapshot in time for what is a steadily evolving technology.

I hope this chart will indirectly give you some insights into where the field may be headed. But before I comment on that, let me just note that this chart — although very different in form — is complementary to the Power Management IC Wallchart we published last year in conjunction with the Power Sources Manufacturers Association (PSMA). For that first chart, the PSMA supplied the “family tree” of power management and power IC circuit functions that are available across the industry.

This IC packaging chart was developed in a similar spirit: Like its predecessor, it's meant to give designers a broad overview of power chip packaging options — or at least the most popular ones. Much of the data is derived from our surveying the offerings of different power IC vendors.

The wallchart lists package styles, typical pin counts and dimensions, and some of the popular functions available in the different styles. A rough order within the chart suggests a few of the trends such as the migration from leaded through-hole packaging to leaded surface-mount and then on to so-called “leadless” package styles, arrays and chip-scale devices.

In addition to shrinking footprints, there is the trend of lower package profiles. Also, you may notice a flow from low- to high-pin counts and from single-die to multi-chip, and even system-in-package devices. Some of these trends may not seem so important in your particular application. But given the symbiotic relationship between packaging and circuit performance and integration, don't lose sight of the possibility that these industry trends in chip packaging could one day help you achieve power-system design goals you once thought were out of reach.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish