Power Electronics

Optimize PFC Preregulator Designs

For EU applications, PFC front-end techniques, such as the CCM boost converter with average current mode control, are widely used to achieve IEC specifications.

Any off-line power supply rated above 75W must comply with the IEC 1000-3-2 harmonic current requirements to be marketed in the European Union. Active power factor correction (PFC) front-end techniques, such as the CCM boost converter with average current mode control, are widely used to achieve this compliance. PFC front-end control differs from traditional PWM control used in other switchmode power supplies. Many dedicated control ICs are available to address these needs [1].

In terms of power stage design, the main elements are the boost inductor, power switch, boost diode, and output capacitor. You can find inductor design equations in IC application notes [2]. However, the peak current rating of the inductor (at low line, full-load conditions) should account for the variations in the PFC IC multiplier output current. The selection of switches also depends on the peak and rms current through it. Because of the relatively low switching frequency of the PFC front-ends (typically in the 100 kHz range), it's possible to use IGBTs with benefits in conduction losses at high power levels. However, most applications still use MOSFETs, due to their lower switching losses. The power switch and boost diode must be rated at or above 500V (about 20% above the boost output voltage). The boost diode should be an ultrafast reverse recovery type.

The output capacitor is generally the most expensive component in the PFC front-end. Usually, hold up time requirements dictate this capacitor's value. However, you can minimize the ripple current in this capacitor by using leading edge modulation for the PFC stage while the second stage uses trailing edge modulation [2]. Another contributor to improved reliability in the capacitor is the smaller variation in the controller's reference voltage and its ability to respond quickly to load transients.

Multiplier Considerations

The multiplier is the heart of a PFC controller. If everything else is designed and operating properly, yet the multiplier is set up incorrectly, then the system will not achieve good PFC. You can see this if you consider that the multiplier is the reference for the current loop. The current loop tries to force the inductor current to follow the multiplier output. There are three inputs to the multiplier, VAOUT, IAC, and VFF. Multiplier current (IMO) is:

Where:
IAC = Multiplier input current, proportional to instantaneous input voltage
VAOUT = Output voltage error signal
VFF = Average value of rectified line voltage
K = Multiplier gain
Equation (1) highlights the interdependence of different parameters. The design is based around the UCC3817, although the general procedure would apply to many controllers.

A PFC circuit typically operates over the universal line range. In most cases this is defined as 85Vrms to 270Vrms. To allow the multiplier to operate within its most linear region, it's best to limit the IAC to less than 500µA at the peak of high line. Operating with higher currents is possible, but some loss of linearity may occur. The peak of high line is about 382V, so the circuit needs a resistor of at least 764kΩ. The voltage rating of most resistors necessitates the use of two resistors in series — so we'll use two 383kΩ resistors, each rated for 200V.

Next, we must develop VFF. In many ICs, this voltage is derived through a resistor divider connected to the dc side of the bridge. This is the rectified line voltage, so a low-pass filter can remove the 120 Hz component. Usually, a two-stage filter improves the transient response.

In most power circuits, cost is an important system driver. Since line voltage information is already available through the IAC pin, you can use that signal and eliminate the two-stage filter tied to the line. This is done in the newer BiCMOS PFC controllers, such as the UCC3817 and UCC38500. This technique divides IAC by two (to keep IC currents low) and mirrors over to the VFF pin (Fig. 1, on page 34).

You need to determine the amount of attenuation before designing the low-pass filter for VFF. The allowable distortion budget drives the attenuation. To achieve 3% total harmonic distortion (THD), it's typical to allow the feedforward circuit to contribute 1.5% third harmonic distortion to the input waveform [2]. This leaves 0.75% for the voltage loop and 0.75% for all others sources. The rectified line voltage frequency is 120 Hz. The second harmonic content is 66.2% of the average value. Therefore, it needs 1.5/66.2 or 0.022 attenuation.

A handy relationship to remember is that for a signal pole roll-off (20dB/decade), a linear relationship exists between the gain and frequency (Fig. 2). The gain at 120 Hz is 0.022, the gain at the pole frequency is approximately 1. Since we know three out of four variables, the pole frequency is:

A parallel RC circuit implements the filter. The resistor value ensures the voltage on VFF stays within its dynamic range over the full line. At low line (85Vrms), we want the multiplier to start entering the power-limiting region [1]. The dc current through the rms resistor is IAC divided by 2 times 0.9. The 0.9 term is the conversion factor for rms to dc for a full wave rectified signal. In the UCC3817 and UCC38500 control ICs the multiplier starts limiting current when VFF = 1.4V, requiring a 25kΩ resistor. The capacitor required to produce a 2.6 Hz pole frequency is approximately 2.2µF.

You might question whether you can modify this value and how would it impact THD. In practice, a 1µF cap has no measurable impact on THD.

This approach has a slower transient response than the two-stage approach. However, the feedforward term corrects for large variations in line voltage. For a given power supply, the input voltage doesn't instantaneously change from 120V to 240V, so it doesn't require a fast response.

To complete the multiplier setup, you must determine the IMO resistor value. A typical approach for ICs, which incorporates a power-limiting characteristic, is to design for maximum power at minimum line [3]. The key is to pick a multiplier terminating resistor so the multiplier can command sufficient current from the line to satisfy the load. The worst case, or maximum current required, is at low line voltage with maximum load. The typical approach is to use the fundamental multiplier equation and plug in appropriate conditions. Solving Equation (1) at low line gives 360µA IMO.

The IMO pin requires a voltage that when developed across the Rsense resistor translates into the required line current to support the load. For a 250W converter, (low line IINpk is 4.4A) and a 0.25Ω sense resistor, this translates to:

Equation (3) assumes the IC multiplier will supply exactly the desired current for the given inputs. That is, the multiplier behaves exactly like Equation (1).

In reality the multiplier has a tolerance associated with it. Most IC companies specify a minimum and maximum multiplier current at specific operating points. Assume the multiplier has a ±10% variation from the ideal. Calculating how much current you can draw from the line for this reduced IMO, yields 3.91A, which is 10% below what we need. Therefore, we wouldn't be able to supply the full load current. In most cases there's some margin in the Vaout range so the controller can correct for small variations. However, in most cases it's best to design to the minimum multiplier current specification. To ensure you can deliver full power, increase RIMO by 10% over the nominal value. This same analysis should be carried out at high line, to ensure the supply of full power with minimum multiplier current.

Once you find the minimum multiplier resistor, calculate the input power over the “corners” of multiplier operation. The main issue is the maximum power the converter can draw from the line. The choice of power devices and thermal design should account for this. For example, assume there's a +40% variation from minimum to maximum multiplier current. Size the multiplier resistor to supply the required maximum line current at minimum multiplier current. For parts that supply the maximum specified current, line current can be 40% higher than required. This doesn't mean that the line current will be 40% higher. The voltage amplifier will command a lower current so the load remains in regulation. This simply means that in a fault condition, the load can increase to the new level.

The power supply can limit this potential problem. Peak current limit will limit the input current on a cycle by cycle basis, preventing the power stage from experiencing excessive thermal problems.

Control Loops

Design of the voltage and current loops impacts system performance. Both loops can contribute to line current distortion. Several good references go into detail on the theory, as well as the details, of control loop design [1,3].

Designing the current loop is usually the first step after designing the power stage. The main job of the current loop is to force the inductor current to follow the multiplier reference current. The reference current isn't simply a 120 Hz waveform: It's rich in harmonics. This waveform has a high dv/dt around the zero crossings of the line. A current-loop bandwidth of around 10 kHz, for a line frequency of 50 Hz to 60 Hz, is usually adequate.

The simplified current-loop transfer function is:

Where:
VSE = Oscillator voltage peak to peak This has a single-pole response at the usual frequencies of interest. Typically, the 2-pole, single zero error amplifier provides compensation (Fig. 3). Zero placement achieves the desired phase margin and high-frequency pole placement filters switching noise [3].

Trade-offs in the voltage loop design are unique to PFC applications. A fundamental requirement of power balance on the line frequency time scale within the PFC circuit requires the voltage loop's bandwidth to be less than one-half the line frequency. If not, the voltage loop distorts the line current to regulate the output voltage. This requires a trade-off between power factor and transient response.

Since the loop bandwidth is low to begin with, avoid integral compensation due to the further reduction in transient response that a relatively large feedback capacitor will cause. The large feedback capacitor required for integral compensation will limit the error amplifier's slew rate. This is troublesome at start up when the poor transient response can cause a large overvoltage condition. The dc regulation of the output voltage is proportional to the loop gain. With the voltage loop gain set relatively low, the output voltage will widely vary with line and load. Since the load of a PFC circuit is typically another converter, dc regulation normally isn't an issue, and start up transient response can be more of a concern due to voltage stress on the output capacitors.

However, dc regulation is more of an issue in applications where you optimize the downstream converter for a narrow input voltage range, or when you require maximum hold up time. Also, some PFC controllers employ a transconductance amplifier so the IC can incorporate multiple functions, such as overvoltage detection on one pin. The traditional voltage-type error amplifier precludes this, since the Vsense pin isn't proportional to Vout in a closed-loop system. A transconductance amplifier's sense pin gives a true measure of output voltage whether or not the loop is in regulation. However, you compensate a transconductance amplifier by connecting an impedance between its output and ground. Usually, the amplifier's output current capability is insufficient to drive a resistive load unless the desired gain is very high. This implies capacitive loading and hence integral gain. For the transconductance amplifier or the need for tighter dc regulation you can use integral compensation. Integral compensation will provide zero dc error. However, since the power stage has a single-pole, roll-off and the integrator adds another 90° of phase shift at low frequency, you need a zero before the loop crossover frequency.

The main design criteria for the voltage loop is usually reduction of the 120 Hz ripple component being fed back to the multiplier [3]. This is necessary because the ripple at the output of the voltage error amplifier is a major contributor to third order harmonics in the line current. In some cases, however, some increased third order harmonic distortion can be tolerated and traded-off for improvements in transient response.

Peak ripple on the boost capacitor is:

If you allow 1.5% of the ripple to feed back to the multiplier, you can calculate the attenuation required and therefore the error amplifier gain at 120 Hz. Assuming the ripple voltage is 4V, 1.5% is 60mV. Therefore, the amplifier gain (GVEA) at 120 Hz is 60mV/4V or 0.015 or -36dB.

Power stage gain is:

One approach to closing the loop is to use an error amplifier with the same configuration, as we used in the current loop. In this case, we calculate where to place the second pole of the error amplifier by placing it at the loop gain crossover frequency. That is, we know the loop gain response after the zero crossing is a double pole, and we know the gain at 120 Hz, so we can calculate the zero dB crossover frequency.

To maintain adequate phase margin, place the zero well below the pole frequency. If it's placed a full decade below, the voltage loop will have about 45° of phase margin.

Powering the Controller

For any high-voltage input power converter, there's a need to develop a semiregulated bias voltage to power the control IC and other control circuitry. The system architecture and the power requirements of the control IC help determine which option is the most suitable for a given application.

Many systems have separate low-power standby regulators that generate the bias voltage for the controller. This approach allows turning off the main power supply during inactive modes to conserve power. However, the economics of adding a separate power supply need justification. Typically, the bias voltage is a regulated 12V or 15V. To accommodate such systems and ensure the controller turn-on, the maximum undervoltage lockout (UVLO) turn-on threshold of the control IC should be below the minimum regulation point of the bias supply.

When you can't justify a separate standby regulator, the power supply must generate its own bias voltage. In a power supply with PFC, you can derive this bias from an additional winding placed on the boost inductor (shown as Bias Option 1 in Fig. 4, on page 44) or on the transformer of the second stage converter (Bias Option 2). In either case, the initial powering of the IC is done through a trickle charge RC circuit. The bias windings can transfer power only after the switching action has started, which in turn happens only after powering the IC. The start-up time requirement at minimum line voltage, allowable power dissipation in RST, UVLO turn-on threshold, and the start-up current drawn by the IC all influence sizing of RST and CST. For example, lower IC start-up current allows a higher value of RST, or lower value of CST, and leads to lower power dissipation or quicker start-up. The minimum value of RST is determined by the need to start-up at the low line (85V) condition. For example, with a 120kΩ RST and 100µF CST, the time to reach the turn-on threshold of the IC is 3.5 sec with a line voltage of 85V and IC start-up current (IST) of 100µA. This choice results in about 0.5W dissipation in RST. If IST doubles to 200µA, start-up time increases to 4.5 sec unless you lower RST and accept the increase in power loss.

Once the IC turns on, it starts drawing more current for its internal operation, and for delivering the gate charge to the external MOSFET. This current isn't available from the line due to the high value of RST. Thus, it must be drawn from CST. The total energy available from CST is given by 0.5×CST×(V12-V22), where V1 is the UVLO turn-on threshold and V2 is the UVLO turn-off threshold. Before using this energy up, the bias windings should develop sufficient voltage (>V2) to keep the IC switching and the converter running. If t2 is the time required for the bias winding to develop sufficient voltage, the required value of CST is:

Where
Qg = Gate charge required to switch external FET/IGBT
fsw = Switching frequency
Ion = IC operating current
V = Average of V1 and V2.

The values of Qg and Ion should include the second stage converter's numbers, if it's allowed to turn on simultaneously with the PFC stage (usually required with Bias Option 2). Bias Option 2 requires a larger value of CST due to higher values of t2, Qg, and Ion. However, it reduces the complexity as it eliminates the bias winding from the PFC inductor. On the other hand, a key factor in minimizing the required CST value is the IC UVLO hysteresis window (V2-V1). With a large hysteresis, the value of CST can be kept to a minimum, leading to a quicker start-up time. Fig. 5 shows required values of CST as a function of V2 when holding V1 constant at 9.6V for an energy level of 7.25 mJ.

Bias Option 1 provides a well-regulated bias voltage, which is independent of line voltage. When the switch is ON, the bias winding places a voltage proportional to Vin across the capacitor CB1: When it's off, it places a voltage proportional to (Vo-Vin) across CB2. The sum of the two voltages results in a bias voltage (Vcc) proportional to Vo.

References

  1. D. Dalal, J. Noon, “Optimized PFC Controller IC Adheres to Harmonic Specs,” PCIM, April 2001.

  2. L. Dixon, “High Power Factor Switching Preregulator Design Optimization,” Unitrode Power Supply Seminar SEM-700.

  3. Texas Instruments, UCC3817 data sheet.

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