By minimizing switching losses, the ZCS variable frequency forward converter provides high power density and a relatively high operating frequency. As seen in Fig. 1, an LC tank circuit using the transformer leakage inductance and a capacitor in the secondary provides the energy transfer medium between the input and output. By turning on the switch, energy transfers from the input source to the tank circuit capacitor, during which time an approximately halfsinusoidal current flows through the switch. Resonant bidirectional energy flow can't occur because the forward rectifier (D_{F}) only permits unidirectional energy transfer. Switch turnon occurs at zerocurrent, and switch turnoff occurs when the current returns to zero. In this way, transfer of energy from the input to the output of the converter is virtually lossfree.
You can divide each switching cycle into four intervals, T1 through T4, as shown in Fig. 2, on page 48. During T1 interval, Q1, D_{F}, and D_{S} conduct, the transformer leakage inductance stores energy, and the resonant capacitor voltage is zero. In T2 interval, the shunt diode becomes reverse biased and main switch, Q1, and D_{F} continue conducting. Leakage inductance resonates with the resonant capacitor and the T2 interval ends when the leakage inductance current returns to zero. During T3 interval, the semiconductors don't conduct, and the resonant capacitor discharges linearly, releasing its energy to the load. T4 interval starts when the resonant capacitor voltage reaches zero, which causes the shunt rectifier to become forward biased. The total energy transfer per pulse is:
Where:
= Normalized output current
L_{Lkg} = Leakage inductance
N = Transformer turns ratio
ω_{r} =
V_{in} = Input voltage
I_{out} = Output load current
The gain of the ZCS converter is a function of the operating conditions and varies with the input voltage and load current. The average voltage produced during the converter's resonant mode is the result of three variables: Vin, Iout, and F ^{[1]}. The incremental control gain is proportional to the inverse of operating frequency, and the input voltage and output load current set the operating frequency.
The ZCS dcdc power converter block diagram in Fig. 3, on page 48, indicates how the operating switching frequency changes as the operating conditions (input voltage and output current) change. When the input voltage or the output load current changes, the total energy transferred per pulse changes. The operating frequency is directly proportional to the output current and the average voltage at the resonant capacitor, and is inversely proportional to the total energy transfer per pulse.
Analytical prediction of the uncompensated openloop transfer function of the system requires an understanding of the controller used with this converter. The controller (Fig. 4) consists of two amplifiers, one is a lowfrequency, narrow bandwidth, very high gain amplifier — which, in the closedloop system, delivers a signal whose average value is just sufficient to drive the average value of the loop error to zero. The second amplifier is a wide bandwidth, variable gain type whose gain is proportional to the output of the lowfrequency amplifier. Fig. 5 shows the gain vs. frequency characteristic of this controller. The controller's transfer function is:
The lowfrequency highgain amplifier dominates below 1 kHz, and the highfrequency lowgain amplifier dominates above 1 kHz. The high frequency, low gain amplifier provides a constant midband loop gain and a controlled rolloff in gain above 1 MHz, which insures that the gain and phase margins at the crossover frequency are consistent with stable closedloop operation.
Output Filter
The output filter transfer function is:
Where:
w_{of} = Output filter break frequency
The output filter poles are complex conjugates that lie in the lefthalf splane at ω_{of}. An effective nondissipative static resistance, R_{R}, in the resonant mode controls the output filter's Q ^{[3]}:
Where:
fc = Conversion frequency
Llk_s = Secondary leakage inductance of the transformer
The output filter corner frequency is a function of the output filter inductance (L_{out}) and the output filter capacitance (C_{out}). Any variation in the output filter inductance (output filter inductance decreases as the load current increases) and the output filter capacitance causes the output filter corner frequency to change.
Capacitance of some output filter ceramic capacitors varies with the applied voltage (capacitance decreases as the applied voltage increases), which results in a variation of the output filter corner frequency. Capacitance of some tantalum output capacitors vary with frequency, and their ESR is a function of frequency. Fig. 6, on page 50, is a Bode plot of the output filter.
The operating frequency of a ZCS forward converter is a function of the variation of the input voltage and the load current. An antilog error amplifier provides predictable closedloop system performance over a wide range of the operating conditions. The power converter's gain is known when the output voltage and the switching frequency are known; it is inversely proportional with the converter's operating frequency. Fig. 7, on page 50, shows the system's openloop uncompensated Bode plot. Thus, the uncompensated openloop transfer function of the system is:
Where:
G_{OL}=Uncompensated openloop transfer function of the system
G_{ERROR}=Controller transfer function
G_{OF}=Output filter transfer function
G_{ZCS}=Forward converter transfer function
The antilog wideband controller compensates for the gain variation of the ZCS converter. The controller has a midband gain, above 1 kHz, of approximately 34 dB.
You can use a leadlag compensation network to obtain the desired phase and gain margins that improve the stability of the ZCS dcdc forward converter. Also, the leadlag compensation can help restore the lost phase margin when the output filter capacitors have a low ESR that produces a zero at higher frequencies. The openloop compensated system transfer function is:
Here, G_{C} is the transfer function of the leadlag network which, in the frequency domain, consists of a zero followed by a pole. Whether you should add a leadlag compensation network will depend on the predicted phase and gain margins of the openloop system, G_{OL}. Fig. 8 is the compensated openloop plot of G_{OL_comp} (s)
If leadlag compensation does not produce an acceptable gain margin, it may be necessary to add a low frequency RC network. The lowfrequency RC network will have a significant effect on the leadlag pole frequency, but it will have no effect on the leadlag zero frequency. Therefore, use of an RC low frequency network will require a redesign of the leadlag network.
Fig. 8 shows the error amplifier circuit with output voltage divider and single polesingle zero leadlag compensation network. The lower resistor of the output voltage divider (R2) can affect the dc gain of the loop and the dc gain of the closedloop transfer function. Effects of R2 on stability can be significant due to the midband limited gain characteristics of the antilog error amplifier (these effects aren't encountered in the use of conventional error amplifiers).
To determine the effect of the output voltage divider's lower resistor on the loopgain and the leadlag compensation network, we first have to look at the closedloop transfer function:
Where:
G_{CL}=Closedloop transfer function
(Output voltage divider ratio)
When using a single zeropole leadlag compensation network, the pole frequency is a function of R2 while the zero frequency is independent of R2, as can be seen from the pole and zero equations:
R_{C} and C_{C} are the leadlag compensation network components shown in Fig. 9, on page 52. You can see the benefits gained from predicting the openloop phase and gain margins in optimizing the design of the leadlag compensation network in an example, where:
Vin_min=180V
Vin_max=375V
Vo=18V
Io=8.33A
Po=150W
Bode plots of the predicted crossover frequency, phase margin, and gain margin of the uncompensated openloop system at low line, fullload conditions are in Fig. 10, on page 52, and high line, full load in Fig. 11, on page 52. Bode plots of the compensated openloop system at low line, full load are in Fig. 12 and high line, fullload conditions in Fig. 13. Looking at the Table, above, you can see this data listed.
At light load, the conversion frequency decreases and causes stability problems (openloop gain margin attenuation), which requires open — loop gain reduction for stabilization. You can achieve this with a lowfrequency laglead compensation network in parallel with the lower resistor of the output voltage divider.
We measured the openloop phase and gain margins at low line, full load and high line, full load of the above design. The predicted openloop phase and gain at LLFL and HLFL conditions agrees with the measured values as you can see in Figs. 14, 15, 16, and 17.
This algorithm has been coded and implemented in an automated bill of materials design generator program that generates feasible ZCS dcdc forward converter designs for given specifications.
References

Patrizio Vinciarelli and Louis Bufano, U.S. Patent No. 5,490,057, “Feedback Control System Having Predictable OpenLoop Gain.”

Montminy et al, U.S. Patent No. 5,946,210, “Configuring Power Converters.”

Louis A. Bufano, PCIM June 1998, “Gain and Frequency Compensation Optimize Performance of ZCS DCDC Forward Converter.”

IEEE Transactions on Power Electronics Vol. 4, No. 2, April 1989. Pp.205214.
For more information on this article, CIRCLE 334 on Reader Service Card