Each new generation of IC lithography opens up higher performance opportunities, more transistors per unit area, and a higher level of integration. Plus, each generation requires lower operating voltages. While lower operating voltages decrease the power dissipated in each transistor, the increase in the number of transistors increases the total power consumed by a microprocessor chip. The balance between total chip power dissipation and performance or operating frequency determines the operating voltage of any given chip.
For any lithography generation, microprocessor chips dissipate lower power when operated at a lower voltage, but speed and performance go down with operating voltage. The power consumed per chip goes up as new functions are integrated and the transistors per chip increases. The trend of declining voltages and increasing power and current creates a need for high performance voltage regulators to power future generations of microprocessors.
You can see the trends in the semiconductor fabrication technology in roadmaps published by the Semiconductor Industry Association (SIA), as shown in the Table. By 2005, chips will be operating less than 1V, drawing up to 170A. You can draw several points from this data:
- Power is increasing as more transistors are available and more functions are integrated.
- Overall gate capacitance increases due to increased transistor count.
- Assuming similar percentage tolerance for each generation, as the working voltage declines, so does the magnitude of the tolerance window.
- With constant or increased power and declining voltage, current is increasing.
These factors impact the design of voltage regulators. One regulator performance factor not obvious from the SIA data is the increase of current slew rate or di/dt. As the operating frequency of the CPU increases, the dt decreases. High di/dt and tighter regulations require fast response voltage regulators. High current and di/dt require minimization of distribution impedance over a frequency range.
Another factor increasing the di/dt is the use of clock gating and thermal throttling to lower the average power dissipated in a microprocessor. Power dissipation decreases by gating functional blocks off when the software or micro code isn't using that section of a microprocessor. For example, when the microprocessor is doing memory reads, you can turn off the floating-point unit. The impact to the voltage regulator is that the current drawn by the chip is no longer a steady state dc current but a complex ac current waveform based on the micro code being executed. To maintain high performance, the system turns these sections of the microprocessor on and off for a few CPU clock cycles. The current swings can be from a few milliamps to tens of amps, which generates high di/dt. Each of these roadmap trends impacts the design of voltage regulators and the components that go into them.
To maintain accurate voltage regulation (both dc and ac), the transient response of the voltage converter becomes prime importance. The need for fast transient response drives up the switching frequency of the voltage regulator (VR), which requires the use of new VR topologies and requires new or novel control techniques developed for their control.
For power systems operating from 12Vdc bus or lower, the nonisolated multiphase buck regulator is the optimal circuit topology for fast transient response (Fig. 1). Much of the current power supply literature is dedicated to the operation and implementation of these regulators, .
Many of the PWM control chip manufacturers make 2-, 3-, and 4-phase interleaved synchronous buck regulators that operate in the range from 250 kHz to 1 MHz per phase. This topology allows the designer to use small output inductors for maximum slew rate while the interleaving cancels the high ripple current from the small inductors and keeps the output voltage ripple at a minimum. The higher operating frequency seen by the output filter reduces the magnitude of output bulk capacitance needed to meet voltage ripple and transient regulation requirements. The lower value of capacitance needed allows for the use of multilayer ceramic capacitors that have low ESR and ESL to make up the entire filter. A 4-phase, 300 kHz per phase voltage regulator can respond in the order of 5 μs to 6 μs on a current transient. The response time is the time from the current transient event to the minimum dip in voltage where the PWM control chip starts driving a new duty cycle and correcting for the load transient. The response time of the power circuit determines the amount of output capacitance needed to support the full load current and meet the voltage droop specification. However, the regulator needs to respond in less than 1 μs. To increase this time by 3 to 5 times, a multiphase regulator needs to operate in the range of 1 MHz to 3 MHz per phase. This requires improvement of all components within the voltage regulator power train.
One issue with the multiphase buck is as the output voltage declines, so does the duty cycle. With small duty cycle and higher operating frequency, the on time of the upper switch becomes too short to control. The short on time may be the ultimate limit on the performance of the buck regulator. This may lead to the development of new topologies with a higher conversion ratio such as “The Active-Clamp Coupled-Buck Converter”.
You can determine the upper limit on the switching frequency by the losses associated with the switching of power MOSFETs and the ability to control short on times. To achieve efficiencies above 85%, you must optimize power MOSFET switches to operate at high frequencies in the buck regulator topology. This requires optimization of a different set of parameters for the main switch and synchronous rectifier. Several papers detail the analysis of switching losses in the buck circuit, . Future power MOSFET designs must concentrate on reducing the gate charge and capacitance, gate resistance, output capacitance, RDS(on), and optimizing the devices for use in the main switch and synchronous rectifier applications. New ideas in packaging, driver and MOSFET integration, and device layout will ultimately be required for the power FETs to keep pace with future logic voltage regulator requirements.
Dominating the switching and transition losses is the loss in the buck regulator's main switch. You can break down these losses into those resulting from gate charge or switching time. The gate charge losses are associated with:
C=Total gate input capacitance including the “Miller Capacitance”
V=Driving gate voltage
f=Gate drive switching frequency
The transition time is associated with the RC time constant, where R is the driver and polysilicon gate resistance. Reducing the input capacitances (gate charge) reduces the transition times and results in faster turn on and turn off, thus lowering the switching power loss. Reducing the gate resistance (silicided gate vs. polysilicon gate) reduces the delay and the transition time, allowing better timing between the upper switch and the synchronous rectifier MOSFET. The reductions in gate charge can be improved incrementally with improvements in gate geometry and oxide thickness using VLSI manufacturing techniques. Ultimately, to achieve switching frequencies over 3 MHz requires new device layouts such as lateral lightly doped (LDD) MOSFET (Fig. 2) built with silicon-on insulator technology; this overcomes the inherent gate charges associated with the trench MOSFET layout. With the small duty cycle, switching losses dominate the main switch loss, so RDS(on) isn't as critical. The lateral device may be practical in this application.
For optimization, the synchronous rectifier MOSFET needs a different set of parameters. With an output voltage below 1.5V and 12V input, a 15V breakdown rating is sufficient. For the synchronous rectifier, the on time approaches 90% of the switching cycle so the conduction RDS(on) loss dominates, followed by transition and turn off losses and body diode reverse recovery loss. The circuit operation allows zero voltage switching, so the “Miller capacitance” isn't an issue with switching performance. However, dv/dt induced turn on can be a problem, and you must maintain a careful balance between Cdg and Cgs. Operation of the synchronous rectifier circuit requires that there be a small dead time when both switches are off to prevent shoot through. During this dead time the body diode conducts. There can be large power losses associated with body diode conduction. Co-packaging Schottky rectifiers with MOSFET die helps lower this loss. The reduction of gate resistance will improve timing and help lower switching losses. Again there can be incremental improvements in RDS(on), but ultimately new low specific on resistance structures such as accumulation trench (ACCUFET), planar ACCUFET MOSFETs will help further reduce the RDS(on) and lower conduction losses to meet circuit efficiencies while operating at greater than 3 MHz, . Fig. 3 compares conventional DMOS and accumulation MOSFET structures.
Even with improvements in silicon technology, the packaging of power MOSFETs must improve. The 105°C rating of FR4 limits the thermal dissipation. A package that conducts heat into the p. c. board and to the top of the package would allow designers flexibility to add heat spreaders. Today's 6 mΩ to 10 mΩ devices owe about 50% of the RDS(on) to the package resistance. New packaging technology, such as Flip Chip BGA or Chip Scale Packaging is important to work with the vertical device structures. The integration of Schottky rectifiers on the same die as the MOSFET will help reduce the Qrr losses of the body diode. New drive techniques that adapt the gate timing can also reduce the dead time and body diode losses.
You can optimize integrated drivers to the gate structure of the power MOSFETs with which they are packaged, making switching timing more precise and eliminating losses due to over or under driving the gate. Adaptive gate drive can be more precise, since the driver chip can sense the die voltages on the MOSFETs without delays associated with layouts. You can achieve the integration of drivers and FETs in a multichip module (MCM) package or integration of drivers and FETs on a monolithic piece of silicon. The input to the driver can be a logic level digital signal that's easy for non-power supply engineers to implement on motherboards.
Future power MOSFETs need a reduction in total gate charge by a factor of 10 nC from 30 nC to 40 nC to less than 5 nC for the main switch. Reduce gate capacitance from ˜2000 pF to 200 pF. The transition time needs to be reduced from ˜50 ns to less than 5 ns. New packaging and the integration of drivers will help achieve the high-frequency switching requirements. New FET structures or materials such as LDMOS, SIO, SiN, and GAs may be necessary to achieve these improvements in performance.
PWM Control Chips
The PWM control chips must keep pace with the demand for higher operating frequencies. To respond in less than a microsecond to a change in output current or voltage dip, the total delays within the PWM chip must be reduced to less than 100 ns. This requires high-speed op amps and comparator structures in the PWM chip.
The higher current demands of future CPUs will require controllers capable of driving more than four phases. For example, if the optimized MOSFET size for high-frequency operation is a 20A buck power stage, a 100A load will require five phases. If smaller FETs or planar FETs can only carry 10A, you would need a 10-phase controller for the same 100A load. With the advances in low-cost DSP chips, the PWM control chip of the future may become more digital with simple analog interfaces. The combination of digital control-based PWM chips and integrated smart driver-FET combinations would allow for flexibility and functionality not achievable with today's analog-based control chips. Control chips with simple digital outputs would simplify the board designer's job by removing fast high current gate drive layout issues.
Novel loop control techniques that improve transient response of the multi phase topology are needed. For example, variable slope PWM ramp and removal of RS latches in the drivers proposed by Yuri Panov and Milan Jovanovic of Delta Products will help to improve the transient response while maintaining per phase switching frequencies at lower levels. Enhanced control techniques to speed up the response time can help reduce the amount of output capacitance needed to meet transient response requirements. This can lead to considerable cost savings since decoupling capacitors can make up to 50% of the bill of material cost in the typical multiphase regulator.
Control chip and MOSFET manufacturers need to work together to optimize the PWM chips and driver — FET combinations to achieve the required 3 MHz to 5 MHz switching frequencies and fast transient response demanded by advanced CPUs. Yet to be determined is the optimal partitioning between control chips, driver chips and MOSFET chips. Cost and performance will determine the partitioning in the next few years as multiphase designs go into high-volume manufacturing.
The multiphase topology buck regulator improves the transient response over the simple buck regulator by lowering the magnitude of the output filter inductance. The smaller inductor allows faster current slewing from the voltage regulator. Multiphase regulators operating in the range of 1 MHz to 3 MHz require lower inductance on the order of 100s of nH. The low inductance allows for simple 1- or 2-turn structures. New magnetic core material and shapes are necessary to support the future 1 MHz to 3 MHz multiphase regulators. Coupled inductor or tapped inductors will require the commercialization of planar multiwinding structures in a drop-in package. Computer motherboard manufacturers don't have an assembly process to clamp EE cores to the main p. c. board. The target size for a 25A phase inductor is 12 mm × 12 mm and less than 8 mm thick in a surface mount configuration. The magnetic material manufacturers need to work with power supply OEMs and PWM chip companies to thoroughly understand the requirements of the fast response multiphase regulators.
Whereas the power semiconductor industry faces many challenges to improve performance to reach high switching frequencies and fast response times, the capacitor industry and regulator designers face many other challenges in designing the output filter decoupling. High-speed logic circuits require very carefully designed decoupling stages. In the case of the microprocessor the voltage regulator output filter is part of this high-speed decoupling network. If the decoupling stage isn't properly designed, the system may oscillate when the logic circuit switches and pulls high di/dt. The spectral content in the frequency domain of a high-speed current pulse contains significant energy over a wide frequency range. This requires the board designer to design a decoupling network that maintains a low impedance over a very wide frequency range. Several papers have been written over the years for designing these types of networks, , . One of the challenges to designing the decoupling network is many of the parameters are associated with interconnect ESL and ESR, not with the capacitors themselves. Fig. 4 shows a typical filter and decoupling distribution model.
Higher switching frequencies and smaller output filter inductors reduce the magnitude of capacitance needed in the output filter. The typical “bulk” capacitor requirements are dropping from 5000 μF to 8000 μF to 1000 μF to 2000 μF as the switching frequency increases from 300 kHz to 1 MHz. 1000 μF is practically realizable with the 100 μF X7R MLCC capacitors on the market from several vendors. Another issue with traditional electrolytic technologies for bulk filtering is the ESL associated with the wound foil and leaded construction. The fundamental ripple frequency for filter capacitors in a 1 MHz, 4-phase regulator is 4 MHz, which is clearly in the inductive region of the electrolytic capacitor impedance. Fig. 5 illustrates the impedance of various capacitor technologies. The ESL of capacitors is becoming as important as ESR has been in the past to voltage regulator designers and capacitor manufactures are urged to investigate other construction techniques to lower the ESL. The new polymer tantalum type capacitors don't work in this frequency because of the roll off of capacitance with frequency.
Voltage regulator designers must look at the filter design in the frequency domain, not just specifying ESR and capacitance to meet a ripple voltage specification. Capacitor manufacturers need to evaluate packaging options to reduce the ESL for the capacitors to work effectively in the megahertz region. With the transition to higher switching frequencies, the demand for large capacitance multilayer ceramic capacitors will be going up, while the leaded electric type of bulk capacitors will see a drop in demand.
To maintain fast transient response, keep the resistance and inductance of the interconnect between the voltage regulator and the CPU to a minimum. New connector styles with inductance below 400 pH and resistances below 200 μΩ will be necessary in the next few years. These connectors must be compatible with the connection to the substrates in the voltage regulator and onto the motherboard or CPU substrate. It's important to examine low inductance structures, such as interleaved parallel plate transmission lines, etc. A major challenge is how to transition from a transmission line in the connector body to the planar structures of common motherboards and CPU substrates and maintain low inductance. Voltage regulator and system partitioning may help reduce some of the target parameters. If you place a connector between the voltage regulator inductor and the filter capacitors, the inductance of the connector is not as critical as it is summed into the voltage regulator inductor. This partitioning of the capacitors outside of the voltage regulator module makes the regulator design more difficult, since it no longer has control of the output filter capacitors and is dependent on the designer to place the appropriate amount and type of capacitors.
Substrates and P. C. Boards
Changes required for a printed circuit board technology is related to cost-effective ways to deliver higher copper weights on controlled impedance boards. 60A requires approximately 4 oz of copper (2 × 1 oz layers for Vcc, 2 ×1 oz for return). 80A+ requires 6 oz of copper. Cost-effective motherboards with mixed 2 oz power planes with 0.5 oz signal planes in 4-, 6-, 8- layer stacks are necessary to meet high current power delivery.
Semiconductor Industry Association “International Technology Roadmap for Semiconductors: 1999, 1999 Edition,” Austin, Texas: SEMATECH, 1999.
X. Zhou, et al., “Investigation of Candidate VRM Topologies for Future Microprocessors,” IEEE Applied Power Electronics Conf. Proc., pp 145-150, Feb. 1998.
P.L. Wong, et al., “VRM Transient Study and Output Filter Design for Future Processors,” Virginia Power Electronics Center Seminar Proc., pp 1-7, Sept. 1998.
P. Xu, J. Wei, F.C. Lee, “The Active-Clamped Coupled-Buck Converter-Novel High Efficiency Voltage Regulator Modules,” IEEE Applied Power Electronics Conference, pp 252-257, March 2001.
Mitter, C. S. “Device Considerations for High-Current, Low-Voltage Synchronous Buck Regulators (SBR),” IEEE Conference Wescon 1997, Santa Clara, Calif., pp 281-288.
A.Q.Huang, N.X. Sun, B. Xhang, X. Zhou, F.C. Lee “Low-voltage Power Devices for Future VRM,” IEEE Proceedings of 1998 International Symposium on Power Semiconductor Devices & IC, Kyoto, Japan
T. Syau, P. Venkatraman, B.J. Baliga “Comparison of Ultra low Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's,” IEEE Transactions on Electron Devices Vol. 41, No. 5, May 1994, pp 800-807.
M.D. Bobde, B.J. Baliga “Silicon Planar ACCUFET: Improved Power MOSFET Structure,” IEEE Electronics Letters, 11th May 2000 Vol. 36, No. 10, pp 913-915.
Yuri Panov, Milan M. Jovanovic“Design Considerations for 12-V/1.5_5, 50A Voltage Regulator Modules,” IEEE Applied Power Electronics Conf., pp 39-46, Feb. 2000.
A.F. Rozman, K.J. Felhoelter “Circuit Considerations for Fast, Sensitive, Low-Voltage Loads in a Distributed Power System,” IEEE 1995.
R. Redl, B.P. Erisman, Z. Zanksy “Optimizing the Load Transient Response of the Buck Converter,” IEEE Applied Power Electronic Conference 1998, pp 170-176.
L. Smith, et-al “Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology,” IEEE Transactions on Advance Packaging, Vol. 22, No. 3, August 1999, pp 284-291.
For more information on this article, CIRCLE 333 on Reader Service Card