Aflux-balance equation for a forward converter with resonant reset enables a designer to minimize primary MOSFET dc losses and calculate voltage stress on power semiconductors. Forward converter with resonant reset and synchronous rectification has become a popular topology for the isolated VRM with 28V and -48V input voltage. In particular, isolated VRMs with 48V input voltage are becoming attractive for point-of-load (POL) converters. One of the many reasons for this popularity is that a 48V POL converter takes roughly four times less of an input current than its 12V nonisolated counterpart. This is a major advantage, due to the reduction in conduction losses on the motherboard.
Another advantage is the reduction of the actual size of the converter. Lower output voltages and higher requirements for efficiency forces the designer, who is using 12V input bus, to employ more phases. Increasing the number of phases leads to the increase of the number of semiconductors and magnetics, which in turn increases the overall size of the converter. Using 48V bus and transformers allow a limit to the number of phases. Therefore, as the amount of semiconductors and inductors are decreased, so is the overall size of the converter. It also provides significant reduction in input and output ripple current. Although this results in an added cost associated with the isolated transformer and primary switches, the overall reduction in parts count compensates for this extra cost.
There are many topologies used in isolated Vrms[1,3,5]: full- and half-bridge, forward and push-pull converters. Focusing on the forward converter, low cost and high reliability are main features of this topology. In many cases, forward converters use only single switch, which in turn simplifies many problems associated with a flux imbalance and transformer saturation. Even with its simplicity and reliability, this topology has its drawbacks: presumably, the hard switching feature and the complexity of realizing ZVS.
With reference to forward converter topology, there are techniques that permit effective use of synchronous rectification (SR). The most common solution is an active clamp reset. The main advantage for this is the controlled level of voltage reset and the voltage stress on the switching MOSFET — not to mention its straightforward design of a self-driven SR. The drawbacks of this topology are the increasing complexity of driving two primary MOSFETs and the complication of a transformer structure. The disadvantages of a self-driven SR become even more obvious from the wide input voltage range requirements, mainly because voltage on the gate driving windings will change with the wide input range. Since gate and switching losses will be input voltage-dependent, the idea of using active reset becomes questionable.
Thus, one of the widely used topologies is the forward converter with resonant reset [1,4]. The main advantage of this approach is a clear simplicity of application — one switch and a reset capacitor with no reset winding or reset MOSFET. Different aspects of this topology and implementation of SR are described in [2,4]. From reference , you can find the problems associated with the implementation of a self-driven SR. The main drawback is the difficulty of driving a freewheeling secondary MOSFET, especially during the “dwell time.”
Principles of Operation
You can see the forward converter with resonant reset in Fig. 1, on page 50. The reset circuit is actually a reset capacitor Cr. In many cases, the parasitic Coss capacitance of primary MOSFET can function as a reset capacitor. Transformer T is represented by magnetizing inductance Lm connected parallel to ideal transformer with turns ratio N and in series with leakage inductance Llk. There are six major stages to take in turn for the ON/OFF cycle of the forward converter with resonant reset. Fig. 2 illustrates these stages in details.
Stage 1 [To - T1]. Q1 is ON. Output current Io flows through D1, and reflected current Ipr flows trough Q1.
Ipr = Iref + Im. Iref = Io/N
Magnetizing current increases at a rate of
Output current increases at the rate of
Reflected current can be described as
Stage 2 [T1-T2]. Q1 is turning OFF. Voltage across Q1 is increasing, because Cs and Coss are charging to VIN by the reflected current flowing through primary winding. D1 still conducts. Magnetizing and reflected current increases.
Stage 3 [T2-T3]. This stage is characterized by a leakage inductance spike. Leakage inductance, Llk, resonates with Cs and keeps current flowing though still conducting D1. D2 also starts to conduct. Secondary transformer winding essentially shorted at this point in time. Voltage across Q1 increases. During the end of this stage the current through D1 is equal to zero. Voltage stress on primary MOSFET is Vq1 = VIN + Vlk.
Magnetizing current doesn't increase and reflected current sharply drops it value to zero. You should take into account reverse recovery losses of D1 for the efficiency calculation at Stages 2 and 3.
Stage 4 [T3-T4]. Magnetizing inductance resonates with Cr. Cr charges by magnetizing current that drops to zero at the end of this period. At this stage, Q1 experiences voltage stress:
Vq1 = V'lk+Vres
V'lk = Klk × Vlk. Where V'lk is initial voltage value in resonant process and Kkl is coefficient that characterizes participation of leakage inductance spike at Stage 3.
Stage 5 [T4-T5]. Magnetizing inductance resonates with Cr, but Cr discharges and magnetizing current is becoming negative toward the end of this period. Voltage across Q1 drops to Vin.
Stage 6 [T5-T6]. Dwell time. At this stage, voltage across primary and secondary transformer windings are equal to zero. There's a negative magnetizing current that flows through transformer, reflected magnetizing current flows on the secondary through D1. Losses associated with power dissipation on D1 during dwell time should be taken into account at this stage.
Where T is switching period, tcdl is dwell time, and Vfd1 is forward voltage drop on D1.
Fig. 3, on page 54, illustrates real-life process of voltage change across the switching MOSFET in the forward converter with resonant reset. It is clear that phases 2 and 3 are happening fast; overall voltage stress on the MOSFET is at least double of input voltage and maximum voltage occur during the end of phase 5 in a peak of resonant process.
It's important to find a flux-balance equation for forward converter with resonant reset. Flux-balance equation enables designers to minimize primary MOSFET dc losses and calculate voltage stress on semiconductors.
Pr_DC = Ipr_rms2 × Rds_on
Extending duty cycle reduces Ipr_rms and proper selection on MOSFET will minimize Rds_on.
It's interesting to find mathematical expressions for the flux and voltage balance — voltage stress on the primary switch and timing characteristics of the resonant process.
Vlk can be found based on the energy balance.
Vres can be found based on energy balance also.
Throughout ON time, the magnetizing current increases from negative value to positive value; thus, magnetizing current can be calculated using following expression:
At stages 4 and 5, voltage across Cr can be described by the following formula:
Vcs=V'lk+Vres × Sin(ωt)
ω = 2 × π × fr
Where fr is a resonant frequency.
The following equation describes resonant reset at Stages 4 and 5:
V'lk+Vres × Sin(ωt)=0
Where tr is a “resonant time” or time needed to charge Cs to maximum voltage and discharge Cs to VIN.
Flux-balance can be described by the following equation for toff > tr:
There is a clear expression for the right part of the equation and finding the solution for the left part of equation isn't very difficult.
Consequently, flux-balance or volt-second balance for resonant reset converter can be expressed by the following equation:
Mathematical expressions of the flux-balance enable a designer to select transformer parameters and resonant capacitance in a manner so that dc losses and voltage stress on the primary MOSFETs are minimized. The equations delivered above aren't meant to substitute formal circuit simulation. Rather, the intention is to save a designer time on initial phase of choosing components and, in many cases, to give necessary tools for rough estimation of modeling results.
Stage 6 or “dwell time” is important when it comes to efficiency. Keeping resonant time tr reasonably close to toff and dwell time minimal will prevent conduction of reflected magnetizing current during toff by D1.
Employing Synchronous Rectification
You can apply general principles of operation of a forward converter with resonant reset on the converter with MOSFETs replacing diodes on the secondary. A block diagram of such a converter or converter with synchronous rectification is shown in Fig. 4, on page 56.
Control Unit switches MOSFETs Qp (primary), Qr (freewheeling), Qf (forward), based on value of output voltage Vo and reference voltage defined by input VID code. MOSFETs Qp and Qf are switching in phase and MOSFETs Qf and Qr are switching out of phase. One of the algorithms of MOSFET control is described in Reference , but simpler approaches are available.
Christopher Bridge, “The Implication of Synchronous Rectifiers to the Design of Isolated, Single-Ended Forward Converters,” Unitrode Products from Texas Instruments, Power Supply Design Seminar, 2001.
Michael Madigan, Mark Dennis. “50W Forward Converter With Synchronous Rectification and Secondary Side Control,” Unitrode Products from Texas Instruments, Power Supply Design Seminar, 1999-2000.
Bill Andreycak, “Active Clamp and Reset Technique Enhances Forward Converter Performance,” Unitrode Products, Power Supply Design Seminar, 1997.
J.A. Cobos, O. Garsia, J. Sebastian, J. Uceda, “Resonant Reset Forward Topologies for Low Output Voltage On Board Converters,” IEEE Applied Power Electronics Conference, Orlando, Fla., February 1994, pp. 703-708.
Abraham I. Pressman, “Switching Power Supply Design,” ISBN 0-07-052236-7.
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