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The synchronous buck converter has been the topology of choice in PCs and notebook computers for years. This topology provides ease of control and high powerconversion efficiencies at a relatively low cost and within a small footprint. One important consideration in designing a synchronous buck converter is limiting the shootthrough or crossconduction current.
Mathematical and numerical formulae have been derived that allow MOSFET designers and powersupply designers to test the suitability of a specific device for use as a synchronous rectifier in the converter. Several solutions that take into account power MOSFET parasitic inductances and resistances allow a better understanding of this complex phenomenon. This article will demonstrate that the gate inductance tends to make the shootthrough situation worse while the source inductance helps keep the gatesource voltage at a lower level. It will also show the equations that describe the gate voltage in time as a function of all the circuit parameters.
Choosing the Right MOSFET
Shootthrough can be understood by examining the factors that control the induced gatesource voltage when the drain voltage is switched between near ground and inputvoltage levels. This situation is encountered in the synchronous buck topology during the time interval when the top MOSFET is switched on while the gate driver holds the lower MOSFET off.
If the induced voltage is larger than the gate threshold voltage of the lowside (LS) MOSFET, it could be turned on while the highside (HS) MOSFET is also on, leading to excessive power dissipation in both MOSFETs and, ultimately, failure in either one or both devices. By examining the mechanism causing this phenomenon, proper MOSFET selection can be made and cross conduction can be eliminated or avoided.
The first example is the simple equivalent circuit in Fig. 1a, where no parasitic inductances are considered. The analysis addresses only the transition time when the HS MOSFET turns on while the LS MOSFET is being held off by the action of the gate driver. The HS MOSFET does not experience shootthrough when it is turned off.
The gatevoltage rise of the LS MOSFET will be determined by the rate of change on the drain voltage as well as the MOSFET's gatesource capacitance (C_{gs}), the gatedrain capacitance (C_{gd}) and the effective series gate resistance. The effective series resistance is calculated from the driver output resistance and the MOSFET's internal effective gate equivalent series resistance (ESR) R_{g}.
Fig. 1b shows the LS MOSFET in the off state and its equivalent circuit for this analysis. This can be calculated by writing Kirchoff's equations for the equivalent circuit of the LS MOSFET. V_{in} is a voltage source representing the effect of the external circuit as the HS MOSFET turns on. The drain voltage = V_{in} = a·t, where “a” is the rate of change of the drain voltage and “t” is time. Kirchoff's equation for this circuit yields:
Similarly:
Solving equations 1, 2 and 3 provides the value of current through the gate resistor:
The gate voltage = V_{g}(t) = R_{g}·i1(t) is calculated by:
The condition for no shootthrough in a given MOSFET under a given rate of change of the drain voltage “a” can be calculated using Eq. 4. At the end of the rise time, t = T_{r} and V_{cc} = input voltage (12 V to 19 V). At this time, if V_{g}(t)≥V_{gth} (the MOSFET gate threshold voltage), cross conduction occurs. To find the value for the parameter “a” to cause cross conduction, Eq. 4 must be solved by substituting
The solution for the maximum value of “a” in Eq. 5 may be obtained by using a suitable numerical solve function typically found in analysis tools such as in Maple.
The Critical Point
Fig. 3 depicts the gatetosource voltage during switching as a function of time and the gate ESR, R_{g}. One can observe that for R_{g}<0.5 Ω, the gatetosource voltage never reaches the critical value of the gate threshold voltage. The plot of the gate voltage, V_{g}, versus the value “a” and R_{g} is shown in Fig. 4.
The intersection of this curve with the line V_{g} = V_{gth} determines the minimum value of a_{crit}, where cross conduction occurs. Note that in Fig. 4, V_{g} approaches an asymptotic value as “a” approaches infinity. This allows additional simplification of the analysis.
For Eq. 5, let us take the limit of V_{g}(t) as “a” approaches infinity:
where V_{g} is the gate voltage at the asymptotic condition of “a” approaching infinity.
At this point, the conditions for cross conduction can be evaluated as follows: If V_{g} calculated from Eq. 6 is less than the lower MOSFET gate threshold voltage, V_{gth} (i.e. V_{g} < V_{gth}), then no cross conduction is expected. Notice that V_{g} in Eq. 6 is independent of R_{g}, which is to be expected. As “a” gets larger, the impedance of C_{gs} becomes much smaller than R_{g} and it becomes the only determining factor, since both R_{g} and C_{gs} are connected in parallel. Alternatively, if V_{g} > V_{gth}, then cross conduction can be expected at some value of “a”.
Even if a MOSFET meets the condition V_{g}≥V_{gth} in Eq. 6, it still may be suitable for the application as a synchronous rectifier as long as it satisfies Eq. 5 for an actual circuit rise time with a finite value of “a.”
Now, let's examine the shootthrough phenomenon including both the source and gate inductances in the circuit, as in Fig. 2. In order to fully understand the mechanics of shootthrough under these conditions, the equations are calculated below under several conditions of input voltage. In the first case, only the rising edge of V_{d} is considered and the equations are solved accordingly.
Let's write the node equations for Fig. 2:
Where:
V_{m}=maximum drain voltage
t_{r}=driving voltage rise time
C_{gs}=gatetosource capacitance
C_{gd}=gatetodrain capacitance
C_{o}=draintosource capacitance
R_{g}=total gate series resistance
L_{g}=total gate inductance
L_{s}=total source inductance.
The gatedrive voltage is a linear ramp with respect to time t.
Solving the differential equations for nodes 14 obtains all the node voltages as a function of time t. Unfortunately, the resulting equations are too long and complex to fully visualize. Therefore, to completely understand the effects of both the source inductance L_{s} and the gate inductance L_{g}, we can generate a few graphs using these equations to show us the trends.
Fig. 5a shows the shootthrough gate voltage for a rise time of 10 ns and a total drain voltage transient of 19 V. This level is quite realistic and agrees with lab results very well. Fig. 5b is the current in the driving voltage V_{d}. This is the current that usually flows in the HS MOSFET while turning on, adding one further component to the dynamic losses and requiring that the gate driver IC can sink this much current without any significant rise in voltage.
The situation is much more complicated when we drive the LS MOSFET with 19 V at a rise time of 1 ns. As can be seen from Fig. 6b, the current that flows in C_{o} also flows in L_{s}, adding one more complexity to the solution since this current tends to be beneficial from the shootthrough point of view since it tends to raise the source voltage resulting in lower gatesource voltage and, hence, causing no shootthrough. Under the right conditions of L_{s} and L_{g}, we may get a negative gatesource voltage completely blocking any chance of the MOSFET turning on, as shown in Fig. 7.
Fig. 6a represents the gatesource voltage when the rise time is 1 ns. Within the next few years, subnanosecond transitions will be the norm in highperformance dcdc power supplies. Notice that the shootthrough gatesource voltage is much smaller than in the 10ns rise time case because of the effect of C_{o} on the current flowing in the source inductance L_{s}.
On the other hand, Fig. 6b represents the current in the driving voltage V_{d} that, as noted previously, flows normally in the highside MOSFET. This means that the gate driver needs to be designed to sink up to 16 A of peak current. The same 16 A will flow in the HS MOSFET, adding significant amount of losses to the MOSFET's turn on losses. This clearly is an undesirable side effect since a very low source inductance is desirable for fast turn on/off.
As with any engineering problem, a compromise between all of these effects must be reached. To do so, one must fully understand the underlying issues and problems and use this knowledge for the best results. Now that we understand the shootthrough phenomenon with the inclusion of both L_{g} and L_{s}, we need to understand the relative influence of each of these parasitic inductances.
Fig. 8 shows the shootthrough gatesource voltage as a function of L_{g} and L_{s} at the end of the rise time of 1 ns. Clearly, except for very low L_{g} (< 1 nH), the gatesource voltage is dominated by the source inductance L_{s} where the larger L_{s} is, the smaller the gatesource voltage and the less the possibility of the shootthrough occurring.
To further understand this phenomenon, we derived a solution with a single 19V pulse introduced to the drain terminal. Figs. 9 and 10 are the gateground and gatesource voltages. Fig. 9 shows the negative voltage swing when the HS MOSFET turns off, causing no shootthrough. Fig. 9 shows the gatesource voltage in the case of a 10ns rise time. When compared to Fig. 5a showing the gatesource voltage under identical conditions, it becomes evident that measuring the gateground voltage of 2.5 V as in Fig. 10 and predicting the existence of shootthrough based on the fact that the gateground voltage is larger than the gate threshold voltage (V_{gth}) is incorrect. That's because Fig. 5a clearly indicates that the gatesource voltage is about 1.2 V only. Hence, for a MOSFET with minimum V_{gth} of 1.5 V, for example, there will be no shootthrough, though the external observation of the gateground voltage is 2.5 V.
Shootthrough is likely to take place in the device with the lowest L_{s} package, but unfortunately, that means that the dynamic losses in the package with the higher L_{s} will be higher.
For completeness, Fig. 11 shows the complete equivalent circuit of the LS MOSFET on the left and on the right the solution of all three different cases: 1) the complete model with L_{s}, L_{g}, and interelectrode resistances, 2) the case with L_{s} and L_{g} only, and 3) the case with no parasitics.
The gate ESR (R_{g}) is a distributed resistance on the MOSFET die. This means that, depending on a region's position, the effective R_{g} is different from one region to the other. Therefore, some regions bear the full brunt of the shootthrough losses, while other regions have no shootthrough losses at all. Theoretical mathematical and simulation work shows that this is the case.
Several conclusions can be drawn from our analysis. One is that Eq. 5 should be used to evaluate a given MOSFET susceptibility to shootthrough for almost all applications today. Equation 6 should be used for the projected applications of the next few years, where the rise and fall times are in the subnanosecond range.
Another is that the gateground voltage alone does not tell whether shootthrough will take place or not. Rather, the gatesource voltage is the decisive factor. Although this conclusion is obvious, it is not observable in the lab since the source of the synchronous rectifier is always connected to ground. Gateground voltage is usually measured since it is the only available measurement.
Furthermore, source inductance plays a more pronounced role in determining whether shootthrough occurs or not, mainly due to the combined effect of C_{o} and L_{s}. A thorough understanding of the parasitic inductances of all MOSFET packages is mandatory to evaluate the susceptibility of a given MOSFET in a given package to shootthrough in preparation for future sub 1ns switching.
Combining the shootthrough loss mechanism with reverserecovery loss mechanism, it becomes obvious that some loop inductance is mandatory to mitigate the switching losses. Exactly how much inductance depends on the specific circuit, the individual MOSFETs and gate drivers.
Finally, there is a large current component that the HS MOSFET has to deliver to charge all the interelectrode capacitors. This current is dependant on the rise time of the voltage of the junction between the HS and the LS MOSFETs and may become the dominant switched current in the HS MOSFET for rise times below 1 ns.
References

Elbanhawy, A. Effect of Parasitic Inductance on Switching Performance. Proc. PCIM Europe 2003, pp.251255.

Elbanhawy, A. Effect of Parasitic Inductance on Switching Performance of Synchronous Buck Converter. Proc. Intel Technology Symposium 2003.

Elbanhawy, A. Mathematical Treatment for HS MOSFET Turn Off. Proc. PEDS 2003.

Elbanhawy, A. A Quantum Leap in Semiconductor Packaging. Proc. PCIM China, pp. 6064.