Power Electronics

Low-Cost PFC Design Meets Regulatory Standards

Quasi-active PFC architecture improves on the single-powerstage converter with PFC technique, increasing efficiency while allowing implementations of a choice of dc-dc topologies.

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The ac-dc off-line application is one of the most important markets in the switching power conversion arena. Electronic devices and equipment operate off ac sources in one way or another, and in most instances require some type of ac-to-dc power conversion. The simplest and most popular method for converting ac power to dc is via diode rectification circuitry. This is the least expensive ac-dc conversion scheme, but it also causes the highest “pollution” to the ac power network[1]. Used in large numbers, these “low”-power devices can significantly affect the quality of the ac line. This is where government regulations kick in to protect power quality.

There are currently two basic regulations for the ac-dc market. EN-61000-3-2 sets the harmonic regulation standard on any off-line application with power consumption over 75 W. This essentially demands power-factor correction (PFC). In addition, a standby power dissipation limit is set to conserve power when the load is off. Government regulations do not challenge the technology itself. The real challenge is how to meet them in the most cost-effective manner considering the massive quantities of the application. There are many mature architectures/circuitries designed to meet the requirements.

A brief look at the market numbers helps in understanding the significance of this application. Some of the very-high-volume applications that may be subjected to the above regulations include notebook computers, LCD desktop monitors and LCD TVs. More than 45 million notebook computers were shipped worldwide in 2004, and this number is expected to reach 90 million in 2008. LCD desk-top monitors are taking over the tra-ditional CRT and are emerging as the dominant display technology with more than 60 million units in 2004 and expectations to grow to 110 million by 2007. LCD TV shipments were about 7 million units in 2004 and are expected to reach more than 50 million units in 2008. With such large quantities sold in the market, saving even a penny per unit would mean millions of dollars in savings.

Although there are several existing PFC technologies, factors such as large size and weight, poor efficiency and high cost may limit their application in high-volume applications. The proposed alternative PFC design is a cost-effective ac-dc off-line converter architecture with a patented quasi-active PFC technology[2]. Not only does it meet all government regulations with low overall system cost, it also improves system reliability and power efficiency while reducing system weight.

Existing PFC Technologies An ac-dc converter circuit with ideal PFC draws a current that is proportional to the instantaneous voltage of its ac source. With a sinusoidal voltage input, the current drawn should also be sinusoidal and in phase with the voltage. Many PFC technologies have been developed through the years, and they fall into three categories: passive, active and single-power stage with PFC.

The passive PFC circuitry realizes the function with only passive components—an inductor and some capacitors (Fig. 1). It is generally robust and effective, but it is more difficult to achieve low total harmonic distortion (THD). Since the circuit operates at the low line frequency (50 Hz or 60 Hz), the passive elements used are normally bulky and heavy.

Active PFC circuits have at least one active switch. The most commonly used active PFC circuit is based on the boost converter with a feed-forward input voltage loop, as shown in Fig. 2[1]. It shapes the input current to provide a low THD. This technology involves only one active switch while offering other advantages. Due to the use of higher switching frequencies, the size of the passive components needed is significantly reduced when compared to the passive PFC circuits.

Its inherent drawbacks include lower overall power-conversion efficiency due to the added switching stage and associated losses. In addition, the regulation on standby power dissipation poses a greater challenge to the active PFC implementations. Since most of the standby current goes into the active PFC power stage, this approach has a much more complex control scheme and tends to consume more power than other approaches. Also, the addition of the active switch significantly increases the bill of materials (BOM) cost and reduces system reliability.

Considering the advantages and disadvantages of the previous two PFC circuits, the concept of a single-power-stage converter with PFC (Fig. 3) was developed several years ago. This converter is obtained by adding some extra passive components, L1 and D2, to a standard converter stage. The additional components are small because they are selected to work at the converter’s switching frequency. In this approach, the main function of the active switch is to regulate the output power, but it also has the task of helping shape the input current. Because both the input and output currents are controlled by the active switch, the power loss in the active switch is increased and the efficiency of the whole circuit suffers. This is a serious limitation of all the single-power-stage converters.

Another problem with the single-power-stage converter with PFC is the power balance issue. Because only one active switch is controlled in the converter, it is hard to control the input and output power independently; and as a result, it is hard to maintain the dc bus voltage within a desired range. The active switch may also be damaged due to overvoltage. Several solutions to overcome these problems have been presented in the last 10 years. Most of these solutions are tradeoffs between performance and the power balance.

Quasi-Active PFC To overcome the disadvantages of the single-power-stage converter, a new concept of quasi-active PFC is proposed. In most off-line dc-dc converters, the input current is made up of a series of discontinuous current pulses. It is this discontinuous current that allows the quasi-active PFC to function. The quasi-active PFC circuit shown in Fig. 4 improves the efficiency of a single-power-stage converter by preventing the input current or voltage due to the PFC from being added to the active switch. The circuit is comprised of a bridge rectifier (BR), a coupled-inductor with three windings (C_Inductor), three valley-fill diodes (D1, D2 and D3), two dc bulk capacitors (C1 and C2), a resonant capacitor (CR) and a discontinuous input current power load, such as a buck, a buck-boost, a forward, a flyback or a resonant converter circuit. In the proposed quasi-active PFC, the dc-dc converter section is not directly involved in the PFC; it simply offers a driving power by applying a series of discontinuous current pulses. The quasi-active PFC network can be considered one power stage but without an active switch.

The quasi-active PFC network will be analyzed by examining its operation in two modes: direct-feed mode and coupled-boost mode. The following analysis corresponds to the positive half cycle of the ac input voltage; a similar analysis applies to the negative half cycle.

Direct-feed mode. During the direct-feed mode, the output voltage of the rectifier bridge is higher than the voltage on each dc bulk capacitor C1 or C2, but less than the sum of voltages on both capacitors. As the load current flowing through the PFC changes from zero to a fixed value, the input line will feed the energy directly to the load and the resonant capacitor CR through the rectifier and the winding L1 of the coupled inductor, which stores a portion of the total energy. As the load current changes back from the fixed value down to zero, the energy stored in L1 will be released to the resonant capacitor CR and the two bulk capacitors C1 and C2 through D3, charging them up. Because the output voltage of the bridge rectifier is less than the sum of the voltages on the two dc bulk capacitors, the charging current through L1 will decay.

Coupled-boost mode. During the coupled-boost mode, the instantaneous rectified voltage is lower than the voltage on each dc bulk capacitor. As the load current changes from zero to a fixed value, the resonant capacitor CR releases the stored energy and its voltage decreases. When the voltage on CR falls below the voltage on C1 and C2, the energy stored in C1 and C2 will be released to the parallel combination of the load and the resonant capacitor. Current passes through the windings L2 and L3 of the coupled inductor storing the energy. L2 and L3 resonate with the capacitor CR.

As the load current changes from the fixed value down to zero, the windings L2 and L3 continue to resonate with CR, whose voltage increases. As the reflected voltage of L1 is less than the voltage across L2 and L3, the diodes D1 and D2 turn off and the stored energy in the windings L2 and L3 is transferred to the winding L1. The energy stored in L1 will be released to the resonant capacitor CR and the bulk capacitors C1 and C2. At the same time, the input power line will also feed energy to CR, C1 and C2.

Since the currents through D1 and D2 are discontinuous and at high frequency, it is possible to use a small high-frequency coupled inductor. The current flowing through D1 and D2 during the coupled-boost interval automatically shapes the input current waveform. It should be noted that the circulating current through the circuit is low. It is the current through L1 that is responsible for the absorption of the energy from the power line when the instantaneous output voltage of the rectifier is lower than that of C1 or C2, thereby increasing the conduction angle of the input rectifier.

It is clear that the reflected load current is the one that flows through the active switch. Due to the presence of the control loop, the current stress on the active switch is determined only by the output load current and is independent of the input PFC current. The voltage stress on the active switch is determined by the maximum dc bus voltage and the topology of the dc-dc converter. It can be limited by selecting a low bus voltage.

The ratio between the direct-feed interval and the coupled-boost interval varies with the ratio between the input voltage amplitude and the voltage on C1 or C2. As the voltage on C1 and C2 increases, the interval of the coupled-boost mode increases, causing the input power to decrease. Conversely, as the voltage on C1 and C2 decreases, the interval of the coupled-boost mode becomes shorter so that the input power increases. Because of the automatic regulation on the coupled-boost mode interval, it is easy to balance the input power and the output power and maintain the dc bus voltage close to the amplitude of the input voltage for all load conditions.

Circuit Design and Experimental Results The quasi-active PFC circuit is a passive circuit driven by the discontinuous current pulses of the following dc-dc converter. To achieve the highest efficiency, the current in the coupled inductor L1 under rated load should be continuous during most of the direct-feed interval and discontinuous during most of the coupled-boost mode interval. In this way, the current in L1 is continuous most of the time and its amplitude is low. Thus, it is possible to avoid the use of a differential inductor and its associated higher cost.

The value of the inductor L1 is determined by the switching frequency and the value of the inductor in the downstream dc-dc converter. When the reflected load current steps up from zero to a certain level, the current in the inductor of the following dc-dc converter increases and the inductor stores the energy. The value of L1 has very little affect on the current through the inductor in the dc-dc converter and the energy stored. This means that the value of the coupled inductor L1 should be smaller than that of the inductor in the dc-dc converter. During the direct-feed interval, the coupled inductor transfers the input energy into the two dc bulk capacitors, which retain enough energy to supply output power during the coupled-boost mode interval. It is clear that for a given inductor current, a higher inductor value will increase the energy stored in the dc capacitors. Based on the previously mentioned requirements, the value of inductor L1 can be chosen to be between one-third and one-fourth that of the inductor LD in the dc-dc converter, that is: L1=kLD where k = 1/4 to 1/3. The turns-ratio of the coupled inductor is chosen as:

where NP , NS and NT (= NS) are the number of turns on the primary (L1), secondary (L2) and the third winding (L3) on the coupled inductor. If the turns-ratio is over 2, the dead time of the input current can be zero. The values of the two bulk capacitors C1 and C2 depend on the dc bus capacitor CD that is used in the regular ac-dc power supply, and they should be double the value of the capacitor CD as: C1 = C2 = 2CD.

The values of C1 and C2 can be larger to have a longer hold-up time. This is a tradeoff with cost that is a system-level design decision.

The resonant capacitor CR controls the instance at which the coupled-boost mode starts. If the value of CR is zero, the coupled-boost mode will prevail until a current is set up in L1. The basic requirement is to have the coupled-boost mode operation only when the instantaneous ac input voltage is lower than the voltage on the capacitors C1 and C2. Based on this requirement, and the values of the reflected load current and the coupled inductor L1, the value of CR can be determined.

A flyback dc-dc power converter was chosen to perform a bench test and verify the quasi-active PFC concept (Fig. 5). The circuit was designed for an output power of 90 W and has an overall efficiency of 86% at the maximum load of 19 V at 4.5 A. The key component values are LD=300 µH (primary winding inductor of flyback transformer), L1=100 µH, CR=30 nF, C1=C2=200 µF/200 V, and the turns-ratio of the coupled inductor is 2-to-1.

The control scheme for the dc-dc converter uses a conventional double-loop control; that is, a current-mode loop plus a voltage-mode loop. The key bench waveforms are shown in Fig. 6. The ac-dc switching power supply has a good power factor of 0.99 and the ac input current is close to a sinusoidal waveform. The output dc voltage has very small, low-frequency ripple (about 200 mV at the double line frequency of 120 Hz).

The quasi-active PFC technology proposed provides passive PFC at the frequency of the downstream switching power supply, and hence, the passive components can be made small in size and light in weight. The voltage stress on the active switch is also low in comparison to other techniques. Since most of the energy is transferred during the direct-feed mode interval, the efficiency of the converter is high. The direct-feed mode interval and the coupled-boost mode interval are adjusted in such a way that the input power and the output power are automatically balanced and the dc bus voltage is regulated around the input ac voltage amplitude.

Since the current through the active switch is equal to the reflected output load current and is independent of the input ac current, the current stress on the active switch and the switching losses are low. As long as the current drawn by the dc-dc converter is discontinuous, the quasi-active PFC circuit will function satisfactorily. Most dc-dc topologies operate with discontinuous current, giving the designer the freedom to choose a suitable dc-dc power topology to implement the quasi-active PFC for the required output power level.PETech

References 1. Dalal, Dhaval. “Boosting Power Supply Efficiency for Desktop Computers.” Power Electronics Technology, pp. 14-23, February 2005. 2. Weng, Da Feng. “Quasi-Active Power Factor Correction Circuit for Switching Power Supply.” U.S. Patent (pending), November 2002.

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