The multichannel, interleaved QSW VRM uses a novel current sensing and sharing technique to improve transient response and minimize supply size.

Advances in microprocessor technologies will impose future powering challenges that require new power supply topologies. Starting with the Pentium, microprocessors are beginning to use nonstandard power supplies of less than 5V. Although microprocessor voltages are decreasing, their current requirements are increasing due to the greater integration density. The 5V plane on the motherboard can't power the microprocessors directly. You need dedicated dc-dc converter voltage regulator modules (VRMs) to power these microprocessors.

Future microprocessors will operate at less than 1V with clock rates beyond 1 GHz, drawing a current significantly higher than before, i.e., from 10A to 50A to 100A. Higher dynamic transients with a significantly increased current slew rate will occur when the microprocessor chip operates from sleep mode to active mode and vice-versa. Moreover, as operation goes below 1V, there will be less tolerance to voltage fluctuations, so regulation must be tighter. These performance requirements pose serious design challenges for the next generation of VRMs, because today's VRMs operate at a lower switching frequency with a higher filter inductance that limits the transient response.

Most of today's VRMs use synchronous buck topology superscript [1-4]. Synchronous buck topology is impractical for future microprocessors because of the huge output and decoupling capacitors needed to maintain voltage regulation. However, a multichannel, interleaved quasi-square-wave (QSW) VRM featuring ultra-fast transient response and high power density could be the solution for future processors superscript [4,5]. Also, the QSW VRM's smaller size makes it possible to integrate it with the microprocessor.

These future requirements are the incentive for developing an 5V-input, 2V/30A-output, four-channel interleaved QSW VRM. Compared with existing conventional VRMs, it has 22 higher output-power, 52 faster transient response and a power density improvement of 62.

Fast VRM Topology As shown in Fig. 1, most of today's typical VRMs use synchronous buck topology requiring a large output filter inductance. This large inductor limits energy transfer speed during a transient, so that the capacitors must store or discharge all the energy that the load needs.

Fig. 2, on page 72, shows the transient response of a synchronous buck VRM. This VRM's input is 5V and its load changes from 0.8A to 30A. From this performance, it's obvious that today's VRM topologies can't meet the 2% transient requirement for future microprocessor loads.

To meet the future microprocessor requirements, you need huge VRM output bulk capacitors and decoupling capacitors (on-board capacitors) to reduce the voltage spike. Using the same circuit shown in Fig. 1, the VRM output capacitors must be increased by three times and the decoupling capacitors by 23 times to meet the 2% transient requirement superscript [3]. Because computer motherboard real estate is relatively expensive and the decoupling capacitors have already occupied almost all the possible areas, today's VRMs will be impractical for future applications.

To overcome the transient limitation occurring in conventional VRMs, the CPES/VPEC (Center for Power Electronic Systems/Virginia Power Electronic Center) proposed a concept of QSW VRM, where it uses a smaller output inductance to increase the energy transfer speed superscript [4,5]. This smaller inductance makes the VRM's transient response much faster.

The QSW VRMs also employ interleaving techniques superscript [4,5]. By paralleling a number of converter modules and phase shifting their drive signals, the interleaving approach reduces the output-ripple current and increases the output-ripple frequency. The reduced ripple current and increased ripple frequency make it possible to reduce the output capacitance to improve the transient response and increase the VRM efficiency. The interleaving techniques also make it possible to parallel the output inductors of the individual modules during the transient. Therefore, you can reduce the output inductance to improve transient response. Other benefits of the interleaving approach include better thermal management and better mechanical performance.

Fig. 3 shows CPES's multichannel interleaved QSW VRM. Fig. 4 shows its transient response. The results show this approach can meet future the transient requirements with reasonable output capacitance.

Control Design Active current-sharing techniques are necessary to achieve a uniform current distribution for the multichannel interleaved VRM superscript [5]. Although this is a common issue in parallel module applications, cost, size, efficiency requirements, and circuit integration make current sensing and sharing techniques more critical in this VRM application.

Traditional approaches use current transformers or resistors to sense current in the individual modules. For low-voltage, high-current VRM applications, current transformers are too bulky and difficult for integration superscript [8], and a sensing resistor reduces converter efficiency significantly.

A novel current-sensing and current-sharing technique was proposed, as shown in Fig. 5 superscript [5]. Here, current-sharing control can be implemented simply in parallel modules without traditional current-sensing disadvantages. It's also easy to integrate as an IC.

As shown in Fig. 5, all parallel modules use a common voltage loop, and the individual modules have a current-sensing RC network and current-sharing control loop. The capacitor voltage signals include the sensed average current information. To simplify the circuit analysis, let's consider only two modules. The same analysis is applicable to any number of modules connected in parallel.

For module 1 and module 2:

V subscript c1(avg)4I subscript o12R13`V subscript o (1)

V subscript c2(avg)4I subscript o22R23`V subscript o (2)

Where: I subscript o14Average current in module 1

I subscript o24Average currents in module 2

R134Equivalent series resistance of output inductor in module 1

R234Equivalent series resistance of output inductor in module 2

The current-sharing control loop is an integrator-type compensator. The error signal from the voltage compensator is used as a reference for all the modules. There's no steady-state error, because the control includes an integrator. Therefore, the RC network outputs, V subscript c1 and V subscript c2 should equal the reference voltage. From Equation (1) and (2), we have:

I subscript o12RI34I subscript o22R23 (3)

From Equation (3), we can see that the current-sharing result depends on the ratio of R13 to R23. When R13 equals R23, the current sharing has very good results and the difference in MOSFET on-resistance and inductance value have no effect on current sharing.

It's easy to control the tolerances of R13 and R23 to less than 10% - especially by using integrated magnetics with p. c. board winding techniques, so you can easily reduce the current-sharing error below 10%. Here, the ratio of R13 to R23 applies - not the absolute value.

Advantages of this approach are: - Does not require precise R, C, and L;

- Variations in Ri1, Ri2, and Li have no effect on current sharing;

- Control design and implementation is very simple; and

- There is no effect on converter efficiency.

Magnetics Design Multichannel interleaving VRMs have more magnetic components than the conventional synchronous buck VRMs. The increased number of inductors in the multichannel, interleaving VRMs increases its complexity.

Integrated magnetic components can reduce this complexity superscript [6]. The two individual inductors of the two interleaving channels can be integrated on a single pair of planar E-E or E-I cores to reduce component count. As shown in Fig. 6, two inductors are built on the two outer legs of the core, and p. c. board traces are used as the inductor windings to reduce the winding and termination losses and to simplify manufacturing. To avoid core saturation, an air gap is necessary on each outer leg. Using no air gap on the center leg, it's possible to decouple the two inductors.

The fluxes generated by the two windings go through tile center leg. Due to phase shift in this interleaving structure, the ac magnetic flux ripple in the center leg reduces. Thus, you can reduce the core loss of the center leg, improving overall efficiency.

By introducing an air gap into the center leg of the core structure, (Fig. 6), further improvement is possible. superscript [7]. The air gap in the center leg introduces coupling between the two inductors, as you can see in Fig. 7.

Represented as a different equivalent inductance in different time intervals, coupling effects can change the inductor current waveforms (Fig. 8). A larger steady-state equivalent inductance L subscript eq1 reduces steady-state current ripple. The equivalent inductance of L subscript eq1 is called "the steady-state equivalent inductance" superscript [7]. As shown in Fig. 8, L subscript eq1.L.

The equivalent inductance of L subscript eq2 determines the dynamic performance of multichannel interleaving VRMs with coupling inductors. Equivalent inductance L subscript eq2 is called "the transient equivalent inductance" superscript [7]. To achieve a fast transient response, a smaller L subscript eq2 is preferred. As shown in Fig. 8, L subscript eq2,L, which means coupling inductors can also improve the transient response of interleaving VRMs.

Steady-state and dynamic performances have contradictory requirements on output inductance. For the non-coupling case, there's only one inductance, which makes it impossible to improve steady-state and dynamic performances simultaneously. For coupled inductors, different equivalent inductors determine the steady-state and dynamic performances of VRMs. Under certain conditions, the steady-state and dynamic performance can be improved by adjusting corresponding equivalent inductance.

The possibility of improving the steady-state and transient performance is the main benefit of applying coupled inductors in interleaved VRMs. Properly designed coupled inductors between interleaved channels can improve both performances.

Additional benefits of using coupling include the mechanical stability of magnetic cores, improved ac and dc flux distribution, and improved current distribution in the p.c. board windings.

Design Evaluation An experimental, 5V input, 2V/30A output VRM prototype, built with the design features described above, has four interleaved modules, each operating at 300 kHz. The selection of the following major components of the VRM power stage includes:

- Top switch: Si4410DY

- Bottom switch: Si4410DY

- Output inductance: 320nH

- Output inductor core is the combination of E18-3F3 with PLT18-3F3

- Each inductor winding has two turns, as shown in Fig. 6, on page 74.

The developed interleaved VRM has excellent current-sharing performance because it uses the proposed current sensing and sharing method. Fig. 9 shows the measured input current for four interleaved modules. When the load current increase from 0.5A to 30A, the difference in the input currents is less than 50mA. The current sharing error is less than 5%.

The prototype achieves a high efficiency, as you can see in Fig. 10. The full-load efficiency is as high as 90%. There's a 2% efficiency improvement by using coupled inductors.

The VRM prototype has fast-transient response and small transient voltage drop. Fig. 11 shows the transient response of the interleaved QSW VRM. As a comparison, you can see the transient response of a conventional synchronous VRM illustrated in Fig. 12.

The Photo, above, shows the conventional synchronous buck VRM. The Table, on page 74, lists a performance comparison between a conventional synchronous VRM and four-channel interleaved QSW VRM. Comparing the conventional and QSW VRMs, the interleaved QSW VRM prototype has 22 higher output power, 52 faster transient response and 62 improvement in power density.

1. Steve Goodfellow and Don Weiss, "Designing Power Systems Around Processor Specifications," Electronic Design, Jan. 1997, pp.53-57.

2. Michael T. Zhang, Milan M. Jovanovic and Fred C. Lee, "Design Consign Considerations for Low Voltage On-board DC/DC Modules for Next Generations of Data Processing Circuits," IEEE Transactions on Power Electronics, Vol. 11, No. 2, March 1996.

3. Pit-Leong Wong, Fred C. Lee, Xunwei Zhou and Jiabin Chen, "Voltage Regulator Module (VRM) Transient Modeling and Analysis," IEEE IAS 1999.

4. Xunwei Zhou, Xingzhu Zhang, Jiangang Liu, Pit-Leong Wong, Jiabin Chen, Ho-Pu Wu, Luca Amoroso, Fred C. Lee, and Dan Y. Chen, "Investigation of Candidate VRM Topologies for future Microprocessors," IEEE APEC 1998.

5. Xunwei Zhou, Peng Xu, and Fred C. Lee, "A High Power Density, High Frequency and Fast Transient Voltage Regulator Module With a Novel Current Sharing and Current Sharing Technique," IEEE APEC 1999.

6. Wei Chen, Fred C. Lee, Xunwei Zhou and Peng Xu, "Integrated Planar Inductor Scheme for Multi-Module Interleaved Quasi-Square-Wave DC/DC Converter", IEEE PESC 1999.

7. Pit-Leong Wong, Qiaoqiao Wu, Peng Xu, Bo Yang and Fred C. Lee, "Investigating Coupling Inductors in the Interleaving QSW VRM," IEEE APEC 2000.

8. Alex Q. Huang, Nick X. Sun, Bo Zhang, Xunwei Zhou and Fred C. Lee, "Low Voltage Power Devices for Future VRM," ISPSD 1998, pp.395-398.