The Athlon Processor poses serious challenges for the associated dc-dc converter with clocks as high as 1.4 GHz and a 133 MHz front side bus. The tight static error band, and the strict transient response requirements mandate a dc-dc converter with robust, time domain reaction to processor “load variations.” The SC2422A input current mode controller, with cycle-by-cycle current sharing, provides an optimal solution while reducing the cost of output capacitors and practically eliminating the need for Oscon capacitors.
This processor has tight dc specifications, so several issues govern the dc-dc converter's response to processor power demands. A major issue is the converter output must stay within a 100mV window during a 0A-45A-output swing. This 100mV band includes output ac ripple and repeatability and converter reference errors over time and temperature. To meet this error band, the output voltage setting, and specifically the converter's droop, must not vary as a function of p. c. board or power MOSFET temperature.
Droop is the difference between the converter output voltage at 0 (or minimum) current and full load. Figs. 1, 2, and 3 demonstrate the need for droop as well as its implementation. The output is intentionally set high, while still inside the dc specification range, and then allowed to droop down as it approaches full load. You can see the advantage of implementing droop and offset during transients. If the peak-peak spike due to transients is 100mV, you can keep it inside the dc accuracy band by offsetting the output +50mV above nominal voltage and allowing it to droop to -50mV below nominal at full load. Because the transient error band is larger than the static error band, implementing droop allows higher spikes, i.e. lower output capacitor cost, without causing an out-of-error band condition. Without droop, a costly bank of low ESR capacitors must absorb the transient spike.
Although some controllers implement droop using power MOSFET RDS(on) sensing, be cautious. As the MOSFET temperature rises, RDS(on) mismatch (typically 20%) and its thermal behavior consume valuable voltage error band tolerance. The controller therefore interprets the RDS(on) variation and mismatch as information regarding the magnitude of load current. Since droop is based on accurately sensing the load current, the RDS(on) mismatch error shows up as output voltage error. To account for this error, the droop using RDS(on) sensing is less than input current sensing, which yields a more temperature-stable current measurement. Less available droop translates into more output capacitors to absorb the spikes — a more costly solution. In the case of the SC2422A, its precision-trimmed current amplifier gain provides an output primarily limited by the accuracy of the current sense resistor (2% to 5%).
Transient Utility Testing
You can implement transient tests on the Athlon processor by running programs that exercise the processor between its two states of “CPU clock stopped” and “full active.” To make matters more severe, during clock-stopped times, the processor can respond to “sneak” execution cycles activated by asynchronous USB (universal serial bus) port. These sneak cycles translate into sharp spikes on the processor core voltage, Vcore, since the processor has to “wake up” for a very short duration, go to full speed and then go back to “sleep.” Current spikes in excess of 50A/µsec are not unusual in the higher speed processors.
You can tune voltage mode controllers for optimum transient response; however, input current mode controllers have an added bandwidth advantage during transients. As the scope plot in Fig. 4 shows, during the transient test of the Athlon processor, the MOSFET gate drive responds to the output load transients faster than a voltage mode error amplifier. Although the SC2422A Error amplifier has a unity gain bandwidth of 5 MHz, the closed loop unity gain crossover frequency of the amplifier is set at around 100 kHz, which is fast.
As seen in Fig. 4, the gate drive (blue trace) responds to the processor core voltage (black trace) as the processor switches modes in less than 1 µsec. It does so by narrowing or widening the gate drive pulses, (compared with respect to the previous drive pulse) while Vcore changes. You can attribute the fast response reflected on the gate drive adjustment to the current loop correction mechanism, which is much faster (pulse-by-pulse) than the voltage loop.
In a voltage mode converter, you will find the response to the processor core voltage changes delayed by an amount inversely proportional to the closed loop bandwidth. If the error amplifier bandwidth is 100 kHz, you can expect a full recovery of gate drive pulse width in about 10 µsec, depending on compensation. At a switching frequency of 200 kHz/phase, that time is equivalent to 4 to 5 gate drive pulses for a single-phase controller.
Long converter reaction times must be compensated with low ESR output capacitance, which “hold the fort” while the error amplifier recovers. The 1.4 GHz processor, on a motherboard utilizing RDS(on) sensing (thus minimum droop) and voltage mode response requires 10 additional 10 µF, low ESR ceramic capacitors to achieve the same transient response.
When running under Windows and to meet Energy Star power saving requirements, the Athlon processor must be capable of entering a standby mode activated from the shut down menu. You can recover from standby via the keyboard, the mouse, or various wake up options such as wake on LAN (local area network) command, etc. Whatever the means of entering or exiting standby mode, the dc-dc converter must meet the voltage error band requirements during such transitions. When the Athlon processor enters the standby mode, its voltage changes from it nominal 1.75V to 1.3V by changing the Voltage Identification (VID) setting to the dc-dc converter controller. Processor clock activity ceases in standby mode, and the processor enters “sleep” mode. However, during the transition, the processor shouldn't experience any voltages that are outside of the transient error band. In addition, the processor must not shut down. This was the case when some controllers issue a gross “power good” violation during such transitions and shut down the converter as a result. In systems using such controllers, you must disable the standby features to prevent the system from resetting. Fig. 5, on page 34, shows the response when entering the standby mode and Fig. 6, on page 35, shows the response when the processor recovers from the standby mode.
The SC2422A is well suited for making the transition to and from standby mode, as it has no automatic shutdown mechanism. This allows the user to decide the condition of the processor core voltage. The converter can be externally shut down via asserting an 11111 VID code or bring the undervoltage lockout (UVLO) pin low. To meet the standby transition specification, add a 2.2 nF to 4.7 nF capacitor between the bandgap voltage, BGOUT pin and VID4. This capacitor forms a voltage divider with the soft start cap, typically 0.1 µF, to make the bandgap reference follow the VID transition, thus preventing the fast error amplifier from undershooting (going into standby) or overshooting (exiting from standby). Alternately, the error amplifier can be overcompensated (overdamped) to prevent such over/undershoot possibilities. You do this at the expense of degrading the system transient response. The additional capacitor is a simple and inexpensive way of meeting the standby transition specs while maintaining optimum transient response.
Fig. 7, on page 36, shows a functional block diagram of the SC2422A. It's a bi-phase current mode controller intended for use with smart synchronous drivers, such as the SC1205 to provide a complete dc-dc converter. It employs input current sensing that guarantees phase-to-phase current matching using a single sense resistor on the input power line. Fig. 8 is a typical dc-dc converter with an SC2422A and two SC1205s.
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