Power Electronics

# Impedance Reflections for Multi-Output Converters

In numerous equipment, a switch-mode power supply (SMPS) delivers various output voltages, each powering different sections. With the introduction of low-voltage circuits such as DSPs, it's not uncommon to find 1.2-V or 1.8-V supplies in addition to the standard 5-V or 12-V rails (for example, in set-top boxes or DVD players).

In most of the cases, the regulation is performed via a feedback loop observing the voltage on a particular point, whereas the rest of the outputs trust the good performance of the transformer to keep on their respective tracks.

In this situation, the stability analysis must encompass the totality of the secondary elements to cover all possible load configurations. Naturally, a traditional paper analysis covering all possible input/output combinations is a difficult and long exercise, where simplifications can also lead to errors. Fortunately, a SPICE simulator can help shorten the stability analysis of a multi-output power supply.

### Simple Reflections

When a resistor is connected to a transformer secondary side, an equivalent resistor is “seen” from the primary side. Fig. 1 shows this typical example, where the turn ratio is normalized to the primary. Normalized means you divide all ratios by the primary ratio. For example, Np:Ns = 10:5, once normalized, becomes 1:0.5.

If the transformer is perfect (Imag50), then we can write, assuming N1 = 1:

1 × I1 = N2 × I2 (1)
but also, V2 = V1 × N2 (2)
or V1/V2 = 1/N2 (3)
Because
I2 = V2/RL (4)
we can plug Equation 4 into Equation 1 to obtain:
I1 = V1/Req = N2 × V2/RL (5)
Req = V1 × RL/N2 × V2 (6)
Thanks to Equation 3, we finally obtain:
Req = RL/N22 (7)

The situation can arise when a load is connected to a secondary winding. In that case, the transformer reduction to a single winding simplifies the analysis. Fig. 2 shows a typical example.

We can first reflect RL2 on the primary side, applying Equation 7:

Req1 = RL2/N32 (8)

Then, we can “push” Req1 over RL1 by still applying Equation 7 but reversed: Req2 = Req1 × N22 = RL2 × N22/N32. Finally, we can write the definition of Req, as defined by Fig. 2b:

Req = RL1//[RL2 × (N2/N3)2] (9)

In place of a resistor, we can reflect a simple capacitor (Fig. 3). In that case, for a sinusoidal excitation, where the capacitive impedance is

Zc = 1/j × C × ω (10)

we can still apply Equation 7:

Ceq = 1/j × C × ω × N22
or Ceq = C × N22 (11)

On Fig. 4a, we also reflect an impedance but to another winding. Applying Equations 10 and 7, we can show that:

Ceq = (1/j × C × ω) × [N2/N3]2 or Ceq = C × [N3/N2]2 (12a)

Note that this equation is the reverse of Equation 9.

With regard to impedances, based on the above, we can write that the reflection of a given impedance to the primary side is governed by:

Zeq = Zload × (N1/N2)2 (12b)

If we assume that N1 = 1, then:

Zeq = Rload × (1/N2)2 for a resistor (12c)

Zeq = 1/(2 × π × f × Cload × N22) for a capacitor (12d)

Zeq = 2 × π × f × Lload/N22 for an inductance (12e)

Because a capacitor is always associated with an equivalent series resistance (ESR), we can update Fig. 3, as Fig. 5a depicts.

The association in series of a capacitor C and a resistor R leads to a complex admittance Y defined by:

if τ = R × C, the network time constant. Its impedance Z is then:

If we apply Equation 7, we find that the equivalent impedance seen from the primary is:

As Fig. 5b shows, paralleling complex impedances is also common because this happens when paralleling two capacitors affected by individual ESRs. Unfortunately, the total impedance obtained via this element combination isn't a simple expression. Let us derive admittance expressions, easier to manipulate when impedances are in parallel.

In the first case, we assume R1 × C1 = R2 × C2. From Fig. 5b, Y1 is the admittance of R1.C1 and Y2 of R2.C2. Therefore, Ytot 5 Y1 + Y2.

By using Equation 13 notation, we can rewrite Equation 16 via:

If τ1 = τ2 = τ, then, the final admittance simplifies to:

which looks like Equation 13 where the capacitor C is the sum of both capacitors (as if paralleled) and the ESR is the value that once combined with (C1 + C2) gives t1 or τ2. This resistance is simply Req = τ1/(C1 + C2), which also leads to Req = R1//R2 (which makes sense because, as F approaches infinity, both capacitors become shorts).

When two series RC networks R1 - C1 and R2 - C2 of same time constants are paralleled, the resulting equivalent series RC network is made of C = C1 + C2 and R = R1//R2.

In the second case, we assume R1 × C1 ≠ R2 × C2. Starting from Equation 16, we can combine after simplification by “p” and neglecting the “1” in the expression:

which differs from Equation 13.

In conclusion, two paralleled RC networks of different time constants do not reduce to a single RC network.

### Simplifying Analysis

A classical situation is the primary regulated power supply. In this application, the auxiliary winding not only provides the Vcc self-supply of the controller, but also offers an image of the output voltage. If the coupling between the two considered windings is of good quality, levels can track each other fairly well.

Fig. 6a depicts a flyback power supply built with the NCP1217 controller from ON Semiconductor. The feedback is ensured by a Zener diode, associated with a low-cost bipolar element Q1. This transistor is necessary because the feedback level must go down to reduce the amount of delivered power. The regulation point is actually D4's anode, the feedback (FB) point, loaded by the circuit Vcc pin.

The exercise will first consist in reflecting all secondary elements to the primary side, reducing the converter to a single output version. By using the simplified equations described previously, we can easily derive the drawing shown in Fig. 6b. The load is reflected as is the controller's consumption, which acts like a resistive element over the FB point. Also, during this reflective process, we consider the dynamic resistor of D1 and D3 close to zero.

To derive the first intermediate step depicted in Fig. 6b:

• Reflect the 4-Ω load to the auxiliary winding: 4 Ω × (0.15/0.166)2 = 3.26 Ω

• Reflect the output capacitor to the auxiliary winding: mF × (0.166/0.15)2 = 1.22 mF.

• Add the chip's power consumption via a simple resistor: 12 V/1 mA = 12 kΩ.
• Combine capacitors and ESR together because both time constants are close: R7//ResrEq, CeqOut + C5 and RVccEq//RloadEq.

• Update the schematic as Fig. 6c shows.

From the final reflection, we can now locate the pole and zero, typical of a flyback converter operated in the discontinuous conduction mode (DCM):

Note that Rload can be derived in a simpler manner. Given the turn ratios, a 12-V output will imply a 12 × (0.15/0.166) = 10.84-V feedback voltage. If we deliver 3 A on the output, it corresponds to 36 W of power. From the auxiliary/FB level, it becomes an equivalent load of:

P = V2/R or Req = 10.842/36 = 3.26 Ω.

### Where SPICE Helps

Thanks to an average SPICE model, testing the SMPS stability becomes child's play. There's no need to reflect capacitors, loads, resistors and so on or to adjust the paralleled combinations — SPICE does it for you automatically. For our case, we need to gather the flyback stage model (current or voltage mode) and then assemble the transformer configuration through the schematic capture.

Our Fig. 6a model thus will become Fig. 7a simulation circuit. Then, by installing a switch on the output and step loading it, we can check the stability of the power supply. Also, we can verify this average configuration by comparing the results delivered by a cycle-by-cycle simulation. Fig. 7b illustrates the cycle-by-cycle circuit, equivalent to Fig. 7a average model.

In this circuit, the power MOSFET has been replaced by a behavioral switch to speed the simulation time. By observing the output voltage when the switch is activated, we can compare the transient response of the average model and the cycle-by-cycle application. Fig. 7c shows both results and confirms the good matching between the average results and the transient model.

This article has shown the importance of running a comprehensive stability analysis of your switch-mode converter, including parasitic elements such as the output diodes dynamic resistance. Failure to do so will lead to major errors in the prediction of the poles and zeroes loci.

Also, when the converter gains in complexity (for example, with the addition of secondary-side inductive filters) the traditional hand analysis becomes complicated and tedious. Fortunately, SPICE offers the necessary flexibility to let you arrange the simulation template to match the real circuit and smoothly run an ac analysis, taking care of reflections and dynamic resistances for you.