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Power-supply management in modern-day compact PCI (cPCI) boards involves not only the sequencing and monitoring of on-board supplies but also must provide hot-swap functionality. The cPCI determines the hot-swap functionality, while the circuit board functionality and the devices used on that board determine the sequencing and monitoring of the supplies. Therefore, designers resort to using multiple ICs to address this complex power-management problem.
Most off-the-shelf hot-swap ICs limit inrush current during card insertion, but they don't respond to power-supply faults local to the circuit board. In order to prevent a power-supply problem local to a circuit board affecting the entire system, it's important to isolate the faulty card from the backplane supply. In addition, designers are required to implement multiple power-supply busses to meet the supply sequencing and tracking requirements of the devices on the board, such as FPGAs, CPUs and ASICs. Multiple reset generators/supervisory chips and various logic functions also are required to monitor all supplies. Thus, it takes multiple devices to implement a complete power-management solution on a cPCI circuit board.
Let's see how a programmable power-management device from Lattice Semiconductor can overcome complexities of the traditional approach to provide a complete power-management solution for a cPCI card, including circuit-board isolation.
As shown in Fig. 1, a typical cPCI circuit board uses a variety of chips, along with its backplane interface and multiple power supplies. In essence, there are three multivoltage devices on this card: a PowerQUICC CPU, ORT42G5 FPGA and the switched backplane ASIC. The table summarizes the power-supply requirement for each multivoltage device. In this solution, the power-management circuit not only limits the inrush current on the -12-V, 5-V, 3.3-V, and 12-V backplane supplies, but it also generates standard cPCI handshake signals during the hot-swap process.
Although the power-supply requirements of each device taken separately are easy to implement, satisfying all these requirements simultaneously on this cPCI board can be quite complex. Apart from the requirements of the individual devices, the design also calls for monitoring power-supply voltages during normal operation. If any supply voltage falls below threshold, the CPU should be reset and the power supply to all devices should be recycled. Overall system power-supply activity can be subdivided into five phases (Fig. 2). The actual power-supply functions during those phases are indicated below the appropriate box.
Managing Multiple Supplies
As shown in Fig. 3, using the programmable power manager IC, a complete power-supply management circuit is implemented on a cPCI circuit board. This programmable power manager, also called Power 1208 (ispPAC-POWR1208) integrates Lattice Semiconductor's ispMACH® CPLD and ispPAC® programmable analog technologies, resulting in a single chip that implements a flexible, cost-effective and convenient solution for the power-management problem. With a supply ruggedized ispMACH PLD at its core, the Power1208 features 12 precision analog threshold comparators with on-chip voltage references for supply monitoring, four noise-immune digital inputs and four open-drain digital outputs for system control interfacing, four programmable (both maximum voltage and ramp rate) high-voltage FET drivers for supply control and four programmable timers with an on-chip 250-kHz oscillator for delay control. The device has been ruggedized to operate in noisy power-supply environments from 2.25 V to 5.5 V.
To meet both cPCI hot-swap specifications and power-supply sequencing and tracking requirements of individual multivoltage devices, the power supply is divided into two sections. The first section, using independent MOSFETs (Q1, Q2), limits inrush current from the backplane. An intermediate power bus, called the “soft-started bus,” is powered through these MOSFETs.
Individual power-supply bricks and MOSFETs power the second section, referred to as the device power bus. The tracking requirement of the PowerQUICC processor can be implemented using a bootstrapping method. However, it results in a non-monotonic ramp of 3.3 V at the CPU's I/O pins. While that non-monotonic ramp is acceptable for the CPU, it doesn't conform to the ORT42G5's power-supply requirement. Thus, we need to route the 3.3 V through another power MOSFET. Likewise, the back-plane ASIC requires the 2.5 V and 3.3 V to track. To address all the requirements simultaneously, we need four power-supply buses in this card, which are:
1.5-V supply, generated using 1.5-V brick for powering CPU's core and the ORT42G5.
3.3 V for the CPU's I/O, which is fed through the MOSFET Q5.
3.3 V for the ORT42G5, back-plane switch ASIC and the remaining ICs on the board, is supplied through the MOSFET Q3 to facilitate monotonic ramp. This supply is enabled along with the 3.3 V of the CPU.
2.5-V brick powered by 5 V, is for the backplane switch ASIC core. MOSFETs Q4 and Q3 implement power-supply tracking between 2.5-V and 3.3-V supplies, as required by the ASIC.
The power-management algorithm is implemented on the embedded CPLD of the Power1208. The following sections describe the algorithm using the 5-phase diagram shown in Fig. 2.
The Power1208 waits for 5-V and 3.3-V inputs to the card to stabilize (using BackPlane_5V_In and BackPlane_3V3_In), and for Logic 0 on BD_SEL# Signal. It can also wait for ±12 V to stabilize. After all conditions are met, the Soft-Start_5V_3V signal is activated, powering the soft-start bus. Programming the gate drive current of the Soft-Start_5V_3V pin of Power1208 controls the current inrush through MOSFETs Q1 and Q2. The En_P_N_12V signal is also activated to enable +12-V and -12-V supply buses.
The 1.5-V brick is turned on first. This will power the core of the CPU and through the Schottky diode (connected between the CPU's I/O and its core), the I/O voltage also closely follows the core voltage, meeting the tracking requirement. At the same time, the power supply to the ORT42G5 core monotonically ramps up.
Once the 1.5 V stabilizes, the 3.3-V supply is turned on through both MOSFETs Q5 and Q3 by the Track_3V3_2V5 pin of the Power1208. Initially, the CPU's I/O pin stays at 1.5 V through the Schottky diode. When the 3.3-V source raises above 1.5 V, the Schottky diode is automatically turned off and the I/O pins follow the 3.3-V MOSFET Q1's output. The exact waveform is shown in Fig. 5. Simultaneously, 3.3 V is applied with a monotonic ramp to both the ASIC and the ORT42G5 devices through the MOSFET Q3. This ensures the power-sequencing requirement of ORT42G5 is met.
By ramping the 2.5 V along with the 3.3 V using the MOSFET Q4 using the same gate drive signal Track_3V3_2V5, the ASIC's power-supply tracking requirement is satisfied. At this stage, all the power supplies are turned on.
During this phase, the Healthy# signal is activated and, simultaneously, a 50-ms timer is started. After that timer expires, the Reset_Out signal is de-asserted. CPU will start executing programs from this time onward.
All power-supply voltages are monitored continuously for faults. When faults occur (i.e., when one of the supplies falls below a defined Vccmin threshold), Brown_out_Int signal is asserted, #Healthy signal is de-asserted, and a 2-ms timer is started to enable CPU to save critical data. After the timer expires, the Reset_Out signal is activated, and device logic transitions to Phase 5. Also, during normal card operation, the Reset_Out signal will be directly controlled by the PCI_RST# signal.
Here, the power supplies for the ASIC and ORT42G5 devices are turned off immediately. In order to meet the power-supply turn-off tracking requirement of the CPU, the following steps must be implemented.
Turn off the 3.3 V to the CPU and simultaneously turn on the shorting MOSFET (Q6), thereby shorting the CPU's I/O pins to core voltage. Wait a few milliseconds for the I/O decoupling capacitors to discharge.
Turn off the core voltage (1.5 V) to the CPU and simultaneously deactivate SoftStart_5V_3V signal decoupling the circuit-board power supply.
As can be seen, the ispPAC power manager device controls the soft-start, sequencing, tracking and monitoring of power supplies efficiently while generating supervisory signals required both by the cPCI bus and on-board components.
Using the Designer Software
Power-supply sequencing and monitoring designs can be implemented on Power1208 devices using Lattice's PAC-Designer version 2.1 software. The PAC-Designer software is an intuitive PC-based schematic design entry and simulation tool. Users can design complex sequencing and monitoring functionality easily using PAC-Designer's LogiBuilder™ feature, which uses a series of easy-to-use pull-down menus to define sequences and conditions to monitor.
To implement the design using the PAC-Designer:
Set the monitoring threshold values for each analog input by selecting the appropriate threshold value from a pull-down menu.
The power-supply ramp rate control is implemented by setting the MOSFET gate drive characteristics for the HVOUT outputs. A pull-down menu sets this as well.
Power-supply sequencing, tracking and supervisory signal generation logic can be defined easily using five point-and-click instructions in the LogiBuilder section.
Verify the completed design using PAC-Designer's waveform simulator.
ispDownload to Power1208 Device — the complete and verified design can be downloaded to the Power1208 device through the device's JTAG port.
Once the interface to the power-supply busses and the MOSFETs are specified, the actual power-supply sequencing and monitoring steps are designed using the LogiBuilder.
The complete power-supply management program is implemented in 14 steps (Fig. 4).
LogiBuilder shows the steps that correspond with the five power-supply phases of power management are:
Step 0 and Step 1 — Waiting for soft-started power supplies to stabilize. Equation 0 in Supervisory Logic window enables soft-start MOSFETs.
Step 2 to Step 5 — Applying the correct power supply to each device.
Step 6 and Step 7 — Pulse stretching of CPU-Reset.
Step 8 — Card normal operation. Step 9 — Low-voltage interrupt.
Step 10 to Step 13 — Turning the power supply off.
This LogiBuilder program is then compiled, and the resulting JEDEC file is downloaded into the ispPAC Power Manager device through its JTAG pins.
The design was implemented and the following oscilloscope screen shots (Figs. 5a and 5b) show that the I/O voltage tracks the core voltage during power-supply ramp up.
The programmable mixed-signal ispPAC-POWR1208 device not only manages all power supplies on the cPCI circuit board, but it also effectively manages the card under power-supply fault conditions and finally isolates it.
Furthermore, the device has well-thought-out resources to meet the requirements of individual circuit-board designs through programmability. The discrete component-based solution, while being inflexible and occupying larger board area, fails to address all aspects of power management. The PAC-Designer software, with its easy-to-use pull-down menus, supports interfacing the ispPAC power manager device to various power-supply arrangements. Power-supply management algorithms can be specified quickly using the LogiBuilder's 5 basic instructions.
Individual Device Power-Supply Requirement
|Device||Supplies Required||Sequencing & Tracking||Additional Requirements|
|PowerQUICC CPU||1.5 V Core & 3.3 V I/O||Voltage difference between core and I/O should not exceed 400 mV during power-up or -down 1.5 V should track 3.3 V.||CPU_Reset should be active for at least 50 ms after the supplies stabilize.|
|ORT42G5 FPSC||1.5 V Core, 3.3 V I/O||Core voltage should be present before I/O voltages ramp. Power supplies should ramp monotonically 1.5 V first and 3.3 V second.|
|Switched backplane ASIC||2.5 V Core, 3.3 V I/O||3.3 V and 2.5 V should track.|
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