Power Electronics
High-Density Power Package for the PC Market

High-Density Power Package for the PC Market

The very high current demands of modern PCs have placed pressures on dc-dc converter design engineers to come up with solutions that meet ever-increasing power demands while fitting in the same PCB footprint. This has resulted in power densities never seen before in the computing industry. The newest generation of packages, such as Ball Grid Array (BGA), allow for the realization of such designs without any sacrifice in electrical or thermal performance.

In this article, designs with BGA are presented, one for the notebook and another for a voltage regulator module, (VRM). These examples demonstrate the extreme flexibility that this package offers the designers; both in heat sinking and in layout freedom.

The BGA Power Package

The BGA power package is developed to overcome some of the serious limitations that hamper standard packages in high-power applications. Specifically, these packages suffer from high levels of parasitic resistance and inductance, as well as mediocre thermal performance. Most traditional packages available for power switches may be heatsinked on one side only. This leads to compromises between the optimum layout and the physical access to the heatsink. In the case of the BGA power package, heatsinking may be achieved from either side of the package, leading to the following advantages:

  • The heat transfer from the die to ambient is maximized.

  • The layout may be fully optimized knowing that heatsinking may be achieved from the bottom of the package through the PCB copper traces or from the top utilizing a heatsink.



For example, the thermal resistance of a 5-mm × 5.5-mm BGA is 0.5°C/W when heatsinked from the top of the package, and 1.3°C/W when heatsinked from the bottom. (It is worth noting that these characteristics are among the best available today for the PC and telecommunications markets.) The BGA family of packages offers one of the best footprints available, because the package outlines are slightly larger than the actual die outlines, thus leading to excellent PCB space utilization and very small real estate for a given dc-dc converter implementation.

Another advantage is that BGA-packaged devices may be clustered together on the PCB. This clustering means a single small heatsink can be used on top, without concern for mounting the MOSFETs to the heatsink by using screws or other fasteners since they are not needed. A simple top contact through an insulator will do the job. Although, clearly, the heatsink itself may to be attached to the PCB using simple springs or screws.

Fig. 1 depicts one heatsinking arrangement where more than one BGA package is cooled using a simple aluminum-extrusion heatsink. Note that the package is still cooled from the bottom through the PCB, which, depending on the copper thickness and the number of layers, may be on its own a very effective cooling mechanism so that no external heatsink is needed. This is exactly the case in the notebook demo board described later in this article.

The package source parasitic inductance plays a major role in determining the rise and fall times of the current in MOSFETs, and consequently, this higher source inductance leads to increased dynamic losses. MOSFET package parasitic resistance adds to the silicon RDS(ON) and invariably results in higher apparent on-resistance since RDS(ON) = RDS(ON) silicon + parasitic resistance. This means that for optimum use of the silicon, we should use a package with the smallest possible parasitic resistance to minimize the power loss.

Drain inductance leads to ringing, especially during high-current switching at fast rise and fall times, leading to inductor losses. In addition, larger EMI also may result from ringing. Gate inductance has a complex relationship with the source inductance in affecting the performance of the switching MOSFET. As a rule, the smaller the gate inductance, the better the performance.

Fig. 2 depicts the temperature rise of the high-side (HS) MOSFET in D2PAK, S08 and BGA packages when heatsinked to a 1-in. × 1-in. 2-oz copper PCB. This comparison assumes an ideal MOSFET is placed in each package (i.e., the ideal MOSFET does not have any conduction or dynamic losses). The x-axis is the drain current (IL), the y-axis is the switching frequency (fs) and the z-axis is the junction temperature rise in °C.

In this case, all of the losses are due to the package parasitic resistance in the form of conduction losses and the package source inductance in the form of dynamic losses. Close examination of Fig. 2 reveals that, while the BGA package offers practically the same temperature rise over the specified frequency and current ranges, both the D2PAK and SO8 exhibit a sharp temperature rise when combining high-switching frequency and high current.

Table 1 shows the results of finite element analysis done on several packages. It depicts the different parasitic inductances and resistance of two power BGA packages compared to a standard SO8. Note that both the parasitic resistance and inductances of 5-mm × 5.5-mm BGA are several orders of magnitude smaller than that of most of the standard packages, resulting in the lower temperatures seen in Fig. 2.

Notebook Demo Board Design

Notebooks demand the highest efficiency possible from the core dc-dc converter, which, in this example, is a synchronous buck converter. This means less power dissipation and less heat needs to be removed from the case. We began our design example based on the requirements of 90 A at 1.4 V.

Component selection must be performed while bearing in mind general considerations like low cost and small footprint. Our circuit considerations included:

  • The MOSFET gate driver should be powerful enough to drive both the high-side and low-side MOSFETs on/off in less than 10 ns. This minimizes the dynamic losses but places higher current demand on the driver.

  • By experimentation, it was decided that one control or HS MOSFET is sufficient, while two synchronous rectifiers or low-side (LS) MOSFETs are needed to minimize the conduction losses, which is the dominant loss factor in the LS switches

  • We chose a 1-µH filter inductor to optimize efficiency. Lower value inductance results in higher ripple current, which leads to higher losses and lower efficiency. An inductor value, which is much higher, will not result in any significant efficiency gains but will result in a narrow control loop bandwidth. This adversely affects the transient response of the converter

    Fig. 3 shows the finished and fully assembled demo board based on our design. The PCB is an 8-layer, 1-oz. copper board that measures 6 in. × 6.5 in. Special attention was paid to the density and compactness of the PCB layout. The MOSFETs selected were Fairchild Semiconductor's FDZ7296, for the control position, and the FDZ7064AS, for the synchronous rectifier. A word about the choice for the synchronous rectifier: The “S” at the end of the part number denotes that this is a SyncFET, a device where a Schottky diode is integrated on the die between the drain and source. This arrangement results in much reduced losses and higher efficiency because of the following:

  • The voltage drop across the Schottky diode is smaller than that of the MOSFET body diode, resulting in lower losses during the dead time.

  • Schottky diodes have no reverse-recovery charge and, hence, the reverse-recovery losses are reduced significantly. But they are not completely eliminated, because at high switching currents, some very small amounts of body diode current still flows. This means some reverse-recovery charge can still be measured but is considerably lower than that measured without the integrated Schottky diode. A typical efficiency gain of 1% to 2% can be achieved using SyncFET devices as compared to the non-SyncFET devices, even with an external Schottky diode connected to the circuit.

    As mentioned before, power-conversion efficiency is probably the single most important parameter in dc-dc converters for notebook applications. Power dissipation in the switching devices is generated due to two major loss mechanisms:

  • Conduction losses, which are the Ohmic losses. These losses stem from the RDS(ON) of the device and may be calculated as Il2* RDS(ON) * duty cycle for the control MOSFET and Il2* RDS(ON) * (1-duty cycle) for the synchronous rectifier where Il is the drain current

  • Dynamic losses, which are the losses due to the device switching. This loss may be calculated as ½*Il*Vin*fs*(tr + tf) where:



Il = Drain current

Vin = Input voltage

fs = Switching Frequency

tr = Current or voltage rise time

tf = Current or voltage fall time.

It is clear from this equation that the dynamic losses are directly proportional to the switching frequency, which is usually selected to achieve the best control-loop bandwidth and hence the best transient response.

Fig. 4 displays the infrared camera output showing temperatures across the PCB. Notice, that the hottest device temperature is 105°C, which is measured in still air without any heatsink at an ambient temperature of 25°C.

Fig. 5 depicts the efficiency measurements performed on the board at both a 16-V and a 19-V input and with a 1.4-V output. As can be seen from the figure, a peak efficiency of up to 93%, and a full-load efficiency of up to 86.5% can be achieved in this design. The board space for the entire converter is about 3.62 in. × 1.25 in. due to the high-density layout techniques utilized in this design. One last check needs to be performed and that is the measurement of the PCB and MOSFET temperatures at full load.

General Considerations

The choice of how many phases to use in a multiphase synchronous buck converter is probably the first decision you will have to make when designing a notebook dc-dc converter. Here are some of the considerations we had to take into account to make this decision:

  • Current per phase. This single parameter will influence the power-train components like the MOSFETs and inductors and will also influence the performance of the converter as expressed by the efficiency. A three-phase design would offer a smaller number of inductors and MOSFETs and is likely to take less PCB real estate. But this approach will increase the conduction losses for a given MOSFET by a factor of (30/22.5)2 or a factor of 1.78. This means we will have to use much larger switching devices to achieve good conduction losses. However, larger MOSFETs have larger Qg and, hence, slower rise and fall times leading to higher dynamic losses.

  • A larger number of phases will distribute the losses and the stresses among a larger number of components. This leads to higher efficiency, lower average operating temperature and better reliability.

  • Other considerations are availability of a heatsink or airflow, limitations on PCB board space, number of layers on the PCB and copper thickness used on the PCB, to name a few.

  • A compromise was found in our example at a four-phase design, leading to a dc-dc converter that delivers excellent efficiency and low operating temperature.



When the four phases are implemented side by side, as can be seen in Fig. 3, the inner two phases are usually running at a higher temperature than the outside two. This problem can be remedied by fine adjustments to the current-sharing pins of the PWM controller. This technique allows for slightly higher phase current for the outer laying phases while slightly reducing the phase current for the inside two, until approximate temperature equality is achieved. This technique also leads to higher reliability and better performance.

VRM: The Design Approach

In the late spring of 2004, the maximum current per phase in multiphase synchronous buck converters for the PC core voltage was hovering around 25 A to 30 A per phase. In the following design example, we decided to push the envelope a little bit further and go with 40 A per phase for the VRM design. We did this for two main reasons. The first reason was to explore the possibility of using such high switched current and to examine its effect on ringing at the switch node as well as the ground plane. The second was from the cost point of view: the larger current per phase meant a lower total number of phases and fewer inductors, MOSFET and gate drivers. This decrease in components pushes the cost down and will result in more efficient PCB space utilization.

Fig. 6 shows the finished module. The choice of the PCB design approach was governed by the following considerations:

  1. Using double-sided component mounting allowed us to mount all the MOSFETs on one side for ease of heatsinking, while the gate driver and the rest of the components were placed on the component side. Placing the gate driver on the opposite side of the MOSFETs allowed the shortest possible connection between the gate driver and the MOSFET gate, which effectively eliminated the major part of the trace inductance.

  2. We chose a VRM board size of 4 in. × 1.2 in. for the smallest practical size. This should be usable in 1U chassis and leading to current density of 50 A/in2.

  3. The use of 2-oz. copper on all layers allowed us to minimize the PCB resistance while using standard copper weight. This avoided incurring high costs for special PCB materials, which would have happened had we chosen to go with the nonstandard 3-oz. or 4-oz. copper.

  4. The number of layers had to accommodate several factors like the lowest possible PCB parasitic resistance and inductance to minimize PCB losses and inductive ringing. We settled on 8 layers.

  5. Vias were widely used to facilitate sharing the high dc and switched currents between multiple layers and because they connect to multiple ground planes.

  6. One of the main points of consideration was the use of several types of vias to facilitate current sharing among different layers without compromise. Tented vias were used under the MOSFETs while regular ones were used everywhere else.



The power-conversion efficiency was measured for one, two, three and four phases to demonstrate the flexibility of this design approach. As can be seen, depending on the application, a minimal number of phases can be used to deliver the desired output power. Fig. 7 shows the results of the lab-efficiency tests performed on the board.

Recent work in the area of power dissipation in synchronous buck converters shows that the source inductance of MOSFETs used for the switching device plays a major role in determining the current rise and fall times of the control or HS switches and can lead to excessive dynamic losses. Since the BGA package has the lowest parasitics of any semiconductor power package in the industry, applications using this package will result in lower losses and higher efficiency.

Table. Finite element analysis comparing packages.
Package Parasitic Resistance (μΩ) Lss (pH) Ldd (pH) Lgg (pH)
SO8 2290 690 318 1800
SO8 wireless 500 477 318 865
5-mm × 5.5-mm BGA 58 6 30 40
2-mm × 2.5-mm BGA 209 10.5 54 32


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