A quasi-square wave switchmode power supply offers many advantages — including a soft EMI signature and a constant efficiency over a broad output load range. However, by nature, a quasi-resonant (QR) supply exhibits a highly variable switching frequency that depends on the input/output operating conditions. Here, we will evaluate the switching frequency at a given operating point and give the designer the necessary insight to dimension his system.
A flyback supply working in the QR mode is just a standard PWM-driven flyback circuit with an added resonating tank. Fig. 1 shows the basic configuration of a converter that could be controlled through a dedicated circuit.
In Fig. 1, the resonating tank is made of Lp — Cp, the primary inductance and the resonating capacitor. When the switch closes, the current builds up in the primary inductance and the drain voltage is close to zero. At the switch opening, the primary current together with Cp dictate the rising slope of the drain voltage. When the leakage inductance is reset, the drain reaches a plateau made of VIN plus the reflected output voltage Vr. Finally, when the core is fully reset, a damped oscillation takes place on the drain and successive “valleys” (minima) appear. If the reflected voltage is selected to be strong enough compared to VIN (ideal is when Vr = VIN), then you can restart the MOSFET with a null drain-source voltage, minimizing all associated capacitive losses. This is called zero-voltage switching (ZVS) operation. The “demag” winding offers an image of the core's flux and helps detect the reset event (when Iprimary = 0). Unfortunately, ZVS can only be obtained if sufficient voltage is reflected on the drain.
Fig. 2, on page 72, portrays a typical signal where the reflected voltage Vr, is too low compared to VIN. When operating on universal mains up to 275Vac, tradeoffs are required to ensure ZVS operation at high line but also to limit the MOSFET BVdss to a reasonable value (a cost-sensitive parameter). For instance, an 800V device is a good choice for allowing QR operation over a large portion of the universal mains, such as on a single output power supply.
Succession of Events
To calculate the operating frequency of a QR converter, you need to account for all the parasitic elements involved in the structure. For example, the total capacitance present over the drain node plays a significant role in slowing down the drain-source signal. Neglecting it leads to a large error, especially if the resonating capacitor has been increased to reduce the dVds/dt and avoid a clamping network. To fully understand the time sequence, Fig. 3, on page 72, shows a QR converter truly operating in ZVS, with the drain-source signal Vds(t), the internal primary inductance current Iprimary(t), and the driver waveshape to detail exactly when the MOSFET is reactivated. Notice that the primary current Iprimary(t) and Vds(t) are in quadrature, switching the MOSFET when Vds(t) is minimum also engenders zero current switching (ZCS). However, if the delay between core reset detection and MOSFET reactivation is too long or too short, then ZVS/ZCS can no longer be maintained and losses increase.
Let's review the events shown in Fig. 3.
The switch closes, forcing Vin across the primary inductance, Lp. The current increases with a slope of:
Upon reaching Ip, the controller dictates the opening of the switch. Therefore:
Ip = Peak current
At the switch opening, the voltage cannot instantaneously increase. The drain capacitive node must be charged with the primary current, Ip. Thus, Vds rises with a slope of:
If we neglect all other capacitance at the drain node, the peak voltage is given by the characteristic impedance of the resonating tank of Lleak and Cp:
The secondary diode starts to conduct when Vds(t) reaches N × (Vout + Vf) + VIN. However, to simplify the analytical results, consider Tleak up to the maximum drain voltage described by Equation (4). This introduces a small error, but not too significant for an off-line SMPS working at moderate switching frequencies. Therefore, combining Equations (3) and (4), we obtain the TL time:
VOUT = Output voltage
Vf = Diode forward drop
N = Np/Ns turn ratio
Lleak = Leakage inductance
Cp = Resonating capacitor
TOFF = The time needed to bring the peak current back to zero through the reflected voltage applied over Lp.
It can thus be defined by:
Without entering into complex calculations, we can see that the valley occurs at half the natural ringing period imposed by Lp and Cp:
However, when using complete calculations, it shows that this result is only valid for lightly damped resonating tanks, which is often the case.
We now have everything needed to compute the switching frequency by summing up all these events and reversing the result: See Equation (8), below.
The unknown equation remains the peak current Ip. To obtain it, we need to start from the classical flyback power transfer formula:
Plug Equation (10) into Equation (8) to obtain a third order equation for Ip: See Equation (11), below.
This third order equation can be examined with a mathematical solver to obtain a rather complicated formula:
Once Ip is known, the switching frequency can be computed via Equation (8).
To ease work for the designer, we have entered this formula into an Excel spreadsheet, NCP1205. By entering the power supply parameters, you can quickly view the evolution of the switching frequency with the selected primary inductance Lp, the input voltage, or select the inductance that brings the desired switching frequency in worst-case conditions, e.g. highest output power and lowest input line.
Fig. 4 is a typical curve given by the spreadsheet for a 30W SMPS featuring the following component values: Lp = 1.4mH, Lleak = 15 µH, VOUT = 16.8V, POUT = 30W, Np:Ns = 16.6, Cp = 1.5nF
To check the calculations, we built a 30W prototype using the NCP1205, a new QR controller featuring a soft frequency foldback with a voltage controlled oscillator (VCO). Fig. 4 compares the frequency variation with the input voltage measured or calculated on the board. As you can see, both curves are in agreement and the high-line error is better than 10%, confirming our assumptions. The complete description of the board is the object of a dedicated application note.
Simplified Controller SPICE Model
The SPICE model offers all necessary features to help validate any calculations. The NCP1205 benefits from a comprehensive model declined in INTUSOFT's IsSpice but also CADENCE's PSpice. However, incorporating all the elements that make the controller precisely reflect the real part (e.g., a VCO for frequency foldback) complicates the model and hampers the simulation time.
To quickly validate and iterate component values, a simplified model has been derived. Fig. 5 depicts how to use it in a ZVS quasi-resonance configuration. The model directly drives a MOSFET and does not bother with quiescent or operating current, under voltage lockouts, etc. but simply focuses on the system: a QR configuration with a resonating capacitor Creso and a transformer affected by a 1:0.06 ratio.
Two simplified models are available: FreeRunDT, which integrates a programmable minimum TOFF to clamp the maximum switching frequency and FreeRunNDT, which does include such a clamp. A complete 1.5 ms run takes 15s on a 1 GHz processor, giving the right speed flexibility to explore different value associations for turn-ratios, peak currents, primary inductance, etc. As usual, this model is available for both PSpice and IsSpice versions.
As shown in Fig. 6, when all parasitic elements are correctly assessed and reflected back the model, good agreement between simulated and measured curves isn't too difficult to obtain.
The author thanks his colleagues François Lhermite and Joël Turchi for fruitful discussions related to quasi-resonant converters. Thanks also to Laszlo Huber from Delta Electronics for his comments during the experiments.
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